Derived clock domain

[fpgaasicdesigner]

Hi,

I'm doing a CLOCK_2 from dividing CLOCK_1.

Then I register the data coming from CLOCK_1 with CLOCK_2

I guess the rising edge of CLOCK_2 and the data coming from CLOCK_1
are exactly aligned so will give me a hold timing error

I used:
create_generated_clock -name CLOCK_2 [get_pins clock_2_reg/Q] - source
CLOCK_1 -divide_by 8

Is it enough for having a good P&R ?

 

[Muzaffer Kal]

On Thu, 8 Apr 2010 11:56:25 -0700 (PDT), fpgaasicdesigner
<fpgaasicdesigner@gmail.com> wrote:

Hi,

I'm doing a CLOCK_2 from dividing CLOCK_1.

Then I register the data coming from CLOCK_1 with CLOCK_2

I guess the rising edge of CLOCK_2 and the data coming from CLOCK_1
are exactly aligned so will give me a hold timing error

I used:
create_generated_clock -name CLOCK_2 [get_pins clock_2_reg/Q] - source
CLOCK_1 -divide_by 8

Is it enough for having a good P&R ?

I am assuming you're generating the divided clock by actually using a
register based counter. This is OK for an ASIC (if you're careful with
CTS) but not preferred on an FPGA.
For an ASIC you may need additional commands to your CTS scripts to
tell it to balance generated clock, especially if you do a CTS from
the main root of CLOCK_1.
For an FPGA this maybe enough initially but if STA tells you that
there are hold problems, you can do the divide in a DCM/PLL and align
the edges of the two clocks to fix it if FPGA PAR hold fixing can't
clean it up completely.
--
Muzaffer Kal

DSPIA INC.
ASIC/FPGA Design Services

http://www.dspia.com