Depth of logical Circuit

[Richard]

Hi all,

I sythesised (with Xilinx ISE) some complex logic circuit just
consisting of AND and XOR gates and I am wondering if there is any way
I can identify in the post-sythese report the depth of the circuit in
number of gates, ie. the number of logical gates that make up the
critical path.

Would be great if somebody could me help me out with this one!

Richard

 

[Brian Drummond]

On Thu, 23 Jun 2011 06:31:33 -0700, Richard wrote:

Hi all,

I sythesised (with Xilinx ISE) some complex logic circuit just
consisting of AND and XOR gates and I am wondering if there is any way I
can identify in the post-sythese report the depth of the circuit in
number of gates, ie. the number of logical gates that make up the
critical path.

Would be great if somebody could me help me out with this one!

Richard

Run the timing analyser. After synthesis it will use estimated timings;
after place and route it will use accurate timings derived from the
routing.

It will give details of the logic depth ( in LUTs rather than gates ) of
the slowest n paths, according to the options you use to run it.

- Brian

 

[Richard]

Run the timing analyser. After synthesis it will use estimated timings;
after place and route it will use accurate timings derived from the
routing.

It will give details of the logic depth ( in LUTs rather than gates ) of
the slowest n paths, according to the options you use to run it.

Cheers Brian, I did what you suggested with the following simple
boolean circuit:

library ieee;
use ieee.std_logic_1164.all;
entity test is
port
(
a : in std_logic;
b : in std_logic;
c : in std_logic;
d : out std_logic
);
end test;

architecture struct of test is

signal t : std_logic;

begin

t <= a and b;
d <= c xor t;

end struct;

Of course you would expect here to see somewhere a logical depth of
two logic gates, (or in LUTS one LUT should do the trick).
However, when I check the timing report I get the following
information:

INFO:Timing:2698 - No timing constraints found, doing default
enumeration.
INFO:Timing:2752 - To get complete path coverage, use the
unconstrained paths
option. All paths that are not constrained will be reported in
the
unconstrained paths section(s) of the report.
INFO:Timing:3339 - The clock-to-out numbers in this timing report are
based on
a 50 Ohm transmission line loading model. For the details of this
model,
and for more information on accounting for different loading
conditions,
please see the device datasheet.

Data Sheet report:
-----------------
All values displayed in nanoseconds (ns)

Pad to Pad
---------------+---------------+---------+
Source Pad |Destination Pad| Delay |
---------------+---------------+---------+
a |d | 4.374|
b |d | 4.221|
c |d | 4.162|
---------------+---------------+---------+

Analysis completed

Are there any parameters I have to pass to XST so that it analysis the
logical path in number of LUTS?

Thanks once again!

 

[Richard]

Run the timing analyser. After synthesis it will use estimated timings;
after place and route it will use accurate timings derived from the
routing.

It will give details of the logic depth ( in LUTs rather than gates ) of
the slowest n paths, according to the options you use to run it.

Cheers Brian. I wrote a very simple logical circuit consisting of two
gates just to try these
things out:

entity test is
port
(
a : in std_logic;
b : in std_logic;
c : in std_logic;
d : out std_logic
);
end test;

architecture struct of test is

signal t : std_logic;

begin

t <= a and b;
d <= c xor t;

end struct;

After the place & route I check the timings and get the following
details.

INFO:Timing:2698 - No timing constraints found, doing default
enumeration.
INFO:Timing:2752 - To get complete path coverage, use the
unconstrained paths
option. All paths that are not constrained will be reported in
the
unconstrained paths section(s) of the report.
INFO:Timing:3339 - The clock-to-out numbers in this timing report are
based on
a 50 Ohm transmission line loading model.

Data Sheet report:
-----------------
All values displayed in nanoseconds (ns)

Pad to Pad
---------------+---------------+---------+
Source Pad |Destination Pad| Delay |
---------------+---------------+---------+
a |d | 4.374|
b |d | 4.221|
c |d | 4.162|
---------------+---------------+---------+

Analysis completed

Unfortuantely, nothing is mentioned of how deep the circuit is which
should be one LUT I guess. Anyone
an idea what I am missing?

Cheers!

 

[Ed McGettigan]

On Jun 23, 7:29 am, Richard <sportfre...@gmx.at> wrote:

Run the timing analyser. After synthesis it will use estimated timings;
after place and route it will use accurate timings derived from the
routing.

It will give details of the logic depth ( in LUTs rather than gates ) of
the slowest n paths, according to the options you use to run it.

Cheers Brian, I did what you suggested with the following simple
boolean circuit:

library ieee;
use ieee.std_logic_1164.all;
entity test is
port
(
  a : in std_logic;
  b : in std_logic;
  c : in std_logic;
  d : out std_logic
);
end test;

architecture struct of test is

  signal t : std_logic;

begin

  t <= a and b;
  d <= c xor t;

end struct;

Of course you would expect here to see somewhere a logical depth of
two logic gates, (or in LUTS one LUT should do the trick).
However, when I check the timing report I get the following
information:

 INFO:Timing:2698 - No timing constraints found, doing default
enumeration.
 INFO:Timing:2752 - To get complete path coverage, use the
unconstrained paths
    option. All paths that are not constrained will be reported in
the
    unconstrained paths section(s) of the report.
 INFO:Timing:3339 - The clock-to-out numbers in this timing report are
based on
    a 50 Ohm transmission line loading model.  For the details of this
model,
    and for more information on accounting for different loading
conditions,
    please see the device datasheet.

 Data Sheet report:
 -----------------
 All values displayed in nanoseconds (ns)

 Pad to Pad
 ---------------+---------------+---------+
 Source Pad     |Destination Pad|  Delay  |
 ---------------+---------------+---------+
 a              |d              |    4.374|
 b              |d              |    4.221|
 c              |d              |    4.162|
 ---------------+---------------+---------+

 Analysis completed

Are there any parameters I have to pass to XST so that it analysis the
logical path in number of LUTS?

Thanks once again!

IMHO, the best way to do this is to add a clock to your design,
register the inputs and register the outputs and then place a PERIOD
constraint on the clock in your UCF file.

This will provide a more accurate number for your experimentation
avoiding extra delays caused by the input and output buffers.

You will likely need to turn on the Verbose reporting feature in the
timing analyzer so that paths are reported even when the timing
constraint is met.

Ed McGettigan
--
Xilinx Inc.

 

[Brian Drummond]

On Thu, 23 Jun 2011 07:29:31 -0700, Richard wrote:

Run the timing analyser. After synthesis it will use estimated timings;
after place and route it will use accurate timings derived from the
routing.

It will give details of the logic depth ( in LUTs rather than gates )
of the slowest n paths, according to the options you use to run it.

Cheers Brian, I did what you suggested with the following simple boolean
circuit:

Are there any parameters I have to pass to XST so that it analysis the
logical path in number of LUTS?

Sorry, I assumed the context of a more complete circuit.

Follow Ed's advice : add a clock, and registers before and after the
circuit itself.

Add a timing constraint to the clock.

Now. An alternative to Ed's suggestion to use verbose reporting from the
timing analyzer : reduce the timing constraint period (or increase
frequency) until P&R fails.

Timing analysis will now give the full and gory details of the worst n
paths that failed the timing constraint, including the levels of logic
you are after.

This is logical and sensible tool behaviour; if it passed timing, most
people don't care about the details. But if it failed, seeing the depth
of the logic depth will guide you as to what part of the design must be
improved to meet timing.

(Alternatively, it may show that excessive routing delay comes from poor
placement of one or more components. But that is another story)

- Brian

 

[OutputLogic]

Hi Richard,

Xilinx has netgen tool that can help you with that.

1. running netgen on a post-synthesis netlist will create a gate-level
HDL representation. For example:
$ netgen -w -ofmt verilog -sim <netlist name>.ngc post_synthesis.v

2. running netgen on a post-MAP design file will create a gate-level
HDL with placement information. For example:
$ netgen -s 3 -pcf <your design name>.pcf -sdf_anno true -sdf_path
"netgen/map" -w -dir netgen/map -ofmt verilog -sim <netlist name>.ncd
post_map.v

3. running netgen on a post-PAR design file will create a gate-level
HDL with placement and routing information. For example:
$ netgen -s 3 -pcf <your design name>.pcf -sdf_anno true -sdf_path
"netgen/par" -insert_pp_buffers true -w -dir netgen/par -ofmt verilog -
sim <netlist name>.ncd post_par.v

You can also do it from ISE GUI without using command-line.




Thanks,
Evgeni


======================
http://outputlogic.com
======================

 

[Brad Smallridge]

I haven't done this in a while. Is it still possible to double click
an output in the ModelSim simulator and get a graphical report on all
the logic leading up to that output?

Brad Smallridge
AiVision

I sythesised (with Xilinx ISE) some complex logic circuit just
consisting of AND and XOR gates and I am wondering if there is any way
I can identify in the post-sythese report the depth of the circuit in
number of gates, ie. the number of logical gates that make up the
critical path.