Delta-Sigma in FPGA Limitations...

[Rickster C]

I\'ve been messing with this for a bit and the ultimate limitation seems to me to not be the digital noise in the FPGA, but rather the imbalance in the edge rise/fall times and/or propagation delays.

The digital noise in the FPGA is going to be mostly in the core. The I/Os are the part that matter to the analog portion of the ADC and they have separate Vcco from the core and also one another. I\'ve been planning to dedicate a bank to the ADCs. But the input signals have a 5 volt range and will require a 3.3 Vcco that is ratiometric to the 5 volt supply. It seemed simpler to add a 5 volt level shifter and let that be powered by the sensor 5 volt rail.

So now I\'m looking for the right buffer device and I\'m starting to realize the limitation is the symmetry in the rise/fall times and the propagation delays of the two edges. Buffers are not so good with this having delays of single digit ns, but also lack of symmetry of single digit ns. With 30 ns pulses, that would add up. I thought analog switches might be better, but they are worse with unbalanced switching times being hard to get into the low single digit ns. Many of the parts I find a LVC which require 3.5 volt inputs when powered from 5V.

Anyone know of parts that would be good for this? Would it make sense to run through two buffers at least conceptually balancing the rise/fall times and prop delays? But then the delays start to add up, but that probably doesn\'t matter as much.

--

Rick C.

- Get 1,000 miles of free Supercharging
- Tesla referral code - https://ts.la/richard11209

 

[Lasse Langwadt Christensen]

onsdag den 18. november 2020 kl. 23.27.57 UTC+1 skrev Rickster C:

I\'ve been messing with this for a bit and the ultimate limitation seems to me to not be the digital noise in the FPGA, but rather the imbalance in the edge rise/fall times and/or propagation delays.

The digital noise in the FPGA is going to be mostly in the core. The I/Os are the part that matter to the analog portion of the ADC and they have separate Vcco from the core and also one another. I\'ve been planning to dedicate a bank to the ADCs. But the input signals have a 5 volt range and will require a 3.3 Vcco that is ratiometric to the 5 volt supply. It seemed simpler to add a 5 volt level shifter and let that be powered by the sensor 5 volt rail.

So now I\'m looking for the right buffer device and I\'m starting to realize the limitation is the symmetry in the rise/fall times and the propagation delays of the two edges. Buffers are not so good with this having delays of single digit ns, but also lack of symmetry of single digit ns. With 30 ns pulses, that would add up. I thought analog switches might be better, but they are worse with unbalanced switching times being hard to get into the low single digit ns. Many of the parts I find a LVC which require 3.5 volt inputs when powered from 5V.

Anyone know of parts that would be good for this? Would it make sense to run through two buffers at least conceptually balancing the rise/fall times and prop delays? But then the delays start to add up, but that probably doesn\'t matter as much.

unless you are trying to be clever for the sake of it or save the last fraction of a dollar just get an ADC

it\'ll have a known specified performance and just work

 

[Rickster C]

On Wednesday, November 18, 2020 at 5:39:17 PM UTC-5, lang...@fonz.dk wrote:

onsdag den 18. november 2020 kl. 23.27.57 UTC+1 skrev Rickster C:
I\'ve been messing with this for a bit and the ultimate limitation seems to me to not be the digital noise in the FPGA, but rather the imbalance in the edge rise/fall times and/or propagation delays.

The digital noise in the FPGA is going to be mostly in the core. The I/Os are the part that matter to the analog portion of the ADC and they have separate Vcco from the core and also one another. I\'ve been planning to dedicate a bank to the ADCs. But the input signals have a 5 volt range and will require a 3.3 Vcco that is ratiometric to the 5 volt supply. It seemed simpler to add a 5 volt level shifter and let that be powered by the sensor 5 volt rail.

So now I\'m looking for the right buffer device and I\'m starting to realize the limitation is the symmetry in the rise/fall times and the propagation delays of the two edges. Buffers are not so good with this having delays of single digit ns, but also lack of symmetry of single digit ns. With 30 ns pulses, that would add up. I thought analog switches might be better, but they are worse with unbalanced switching times being hard to get into the low single digit ns. Many of the parts I find a LVC which require 3.5 volt inputs when powered from 5V.

Anyone know of parts that would be good for this? Would it make sense to run through two buffers at least conceptually balancing the rise/fall times and prop delays? But then the delays start to add up, but that probably doesn\'t matter as much.

unless you are trying to be clever for the sake of it or save the last fraction of a dollar just get an ADC

it\'ll have a known specified performance and just work

Yeah, people say that a lot. On one hand, the project lead has told me to save $0.10 when spending that would make life easier. On the other hand the guy who is entering schematics (that\'s how the job was probably described to him, but now he\'s doing various design functions) never saw a Linear Tech part he didn\'t like, including parts we don\'t need. We have a DC input and an SLA battery. So now there is an LT something ($) boost switcher to charge the battery (which doesn\'t do everything the chip it replaces does), LT something ($) to over/under voltage protect the input (which drives circuits that are already pretty well protected by themselves), LT something ($) to switch between the two power sources, LT something ($) to buck the ~12V merged power down to 7.5V to supply the logic. With the switchers it justified separating the power circuitry onto a separate board ($).

So I guess I\'m not sure why I\'m still trying to save the $4 for the ADC except that I know it can be done and done well.

I\'m just asking questions to discuss what I think is an interesting design issue. I wonder why people get impatient with that sort of thing?

BTW, unless I find a better part, the 74ACT244PW seems like a good candidate for the job. The propagation delay is spec\'d equally for both edges and the output drive is balanced. It is a 5 volt part with TTL inputs, so driveable from 3.3 volt I/Os. Yeah, I think a $0.20 part beats a $4 part any day.

The ADC chip has some issues as well. It\'s rather a PITA to program with lots of bytes of setup. We have to program a couple of digital sensors (abs pressure and rel humidity). The interfaces can be awkward like the need to sever power to an I2C device for when it gets bus hung.

--

Rick C.

+ Get 1,000 miles of free Supercharging
+ Tesla referral code - https://ts.la/richard11209

 

[Rick C]

On Thursday, November 26, 2020 at 5:37:15 PM UTC-5, anti...@math.uni.wroc.pl wrote:

Rickster C <gnuarm.del...@gmail.com> wrote:
I\'ve been messing with this for a bit and the ultimate limitation seems to me to not be the digital noise in the FPGA, but rather the imbalance in the edge rise/fall times and/or propagation delays.
Well, \"ultimate\" circuits usually depend on compensation and
calibration. So limits are due to inability to compensate
(or remove via calibration) error. For example short
term drifts may be problematic. In current times it
seems that \"ultimate\" circuits usualy will be IC,
because:
- some good elements are available only as parts of IC
- lower parasitics
- matching of elements
- trimming on IC seem to be significantly less expensive
than trimming of discrete circuits

Some of these issues are mitigated by the circuit design. The C is not relevant since the time constant does not factor into the accuracy of the unit, only that it does not change, so no microphonic ceramic caps. The value of R is also not a factor in the accuracy of the unit, only that it does not change which relates to the relative contributions of the high and low resistance of the driver. This is mitigated by the relative value of the circuit resistance swamping out small variations in driving resistance. However, for a given time constant a larger resistor uses a smaller capacitor which accentuates imbalances in charge injection.

However, it seems that you have concrete circuit in mind
with requiraments that are very far from \"ultimate\".

Not sure what that means really. The requirements are for resolution to 14 bits. With a 10 bit converter the resolution of the signal does not give adequate resolution in the output as a square root function is involved. The current test board has an amplifier to allow the low range to be measured with higher resolution. Measuring the full range with more resolution will eliminate the need for additional amplifiers and ADC circuits. The time window for making the measurement and the clock used provides 17.3 bits of count. No reason to toss any of those bits. The accuracy of the measurements is 2.5%. But accuracy is not resolution and the requirements do not need to match up.

The digital noise in the FPGA is going to be mostly in the core. The I/Os are the part that matter to the analog portion of the ADC and they have separate Vcco from the core and also one another. I\'ve been planning to dedicate a bank to the ADCs. But the input signals have a 5 volt range and will require a 3.3 Vcco that is ratiometric to the 5 volt supply. It seemed simpler to add a 5 volt level shifter and let that be powered by the sensor 5 volt rail.

So now I\'m looking for the right buffer device and I\'m starting to realize the limitation is the symmetry in the rise/fall times and the propagation delays of the two edges. Buffers are not so good with this having delays of single digit ns, but also lack of symmetry of single digit ns. With 30 ns pulses, that would add up. I thought analog switches might be better, but they are worse with unbalanced switching times being hard to get into the low single digit ns. Many of the parts I find a LVC which require 3.5 volt inputs when powered from 5V.

Anyone know of parts that would be good for this? Would it make sense to run through two buffers at least conceptually balancing the rise/fall times and prop delays? But then the delays start to add up, but that probably doesn\'t matter as much.
In other post you mention 74ACT244. AFAIK HC type gate were used
as switches in reasonably precise circuits. OTOH a lot depends
on specific details of your circuit. In post in comp.dsp you
gave some details of your circit (I assume you mean the same
circuit here). To say the truth, I would describe it not as
delta-sigma but as multiple slope convertor.

Not sure why you say that. A slope converter measures the time of charging or discharging a capacitor with no feedback, just a threshold to obtain the measurement. Here the circuit essentially is using a feedback loop to balance the currents feeding the capacitor to maintain a constant voltage. This feedback creates a density modulated pulse stream. That\'s nothing like a slope converter.

You have
integrating capacitor that is connected via resitor to input voltage,
via switch and resitor to either ground or positive supply
and to comparator that compares voltage on capacitor with
rererence voltage. In first order approximation voltage
on capacitor is triangular and we have equality:

V_0/R_0 = MV_1/R_1 + NV_2/R_2 + n(C_1 + C_2)

where V_0 = V_in - V_a is difference between input voltage
and average voltage on the capacitor, V_a is average voltage
on the capacitor, V_1 = V_cc - V_a is difference between
supply voltage and average voltage on the capacitor,
V_2 = -V_a, M is fraction of time when switch is
connected to V_cc, R_1 is sum of resitor and switch
resistance, N is fraction of time when switch is
connected to ground, R_2 is sum of resitor and switch
resistance, n is switching frequency, C_1 is is extra
charge transferred during switching up, C_2 is
extra charge transferred during switching down.
With ideal switches R_1 = R_2 is just resitistance
between integrating capacitor and the switch and
C_1 = C_2 = 0. With non-ideal idealy balanced switch
C_1 = -C_2 so switching error vanishes and switch
resistance just changes scale factor. With unbalanced
switch we still can try to calibrate it out: other
terms are linear so three point calibation can
null switching error term. CMOS chips have switching
characteristics that depend on temperature, so there
are limits to calibration, but one can do better
than magnitide of switching errors would suggest.

Concerning symmetry of switches, I see nothing in
ACT244 datasheet that would claim symmetry. Bounds
are symmetric, but are quite wide so highly
asymetric chip will still stay withing datasheet
bound.

No, there is no spec on balance, but the symmetrical specifications would indicate the design is symmetrical. No reason to expect wide differences. It\'s a good as it will be unless devices are used with balance specs and I found none that would be appropriate. I looked at using analog switches to multiplex voltages and found excessive shoot through. Seems many are designed to make before break. Also the switching times are slow compared to my clock. I\'m giving thought to slowing the clock rate to minimize the injection potential since we have more than adequate resolution.

I have no equipment to measure propagation
delay, but I measured switch resistance for some
chips (both from chinese selers, so possibly fake).
HC00 was reasonably symmetric, in HC04 lower
switch had 3 time lower resistance than high switch.
As I wrote, they may be fake, but resistance was
well within datasheet bounds. BTW: I looked at
HC chips because they are faster and have
lower resistance than cheap analog switches.
And I hoped for better symmetry in HC than
in ACT.

Yes, I found analog switches to be inordinately slow as well. The HC devices are also not very fast and it would be required to use the HCT devices to maintain 3V input compatibility. The ACT was the device with the best spec in the \'T\' category I could find. There are no shortages of \"categories\" when it comes to logic families.

More generaly, charge balance principle (like
in Pease or Wiliams voltage to frequency convertors)
may give better accuracy, because charge is
determined by reference voltage and charging
capactor and depends very weakly on switch
parameters. Of course, drawback is that
you would need two good capacitors.

It\'s also a lot of circuit. The point is to minimize the devices needed and working with the FPGA digital domain primarily. I\'m making one concession of using an external buffer chip for the 1-bit DACs. The FPGA comparator inputs are being used however because it is too much to add a comparator for every ADC in the design. Anything more than the buffer and I might as well use an ADC chip.

I think a lot of people are intimidated by using something that is new to them and no one they know is using it. The various reports focus on the use for applications where high SNR and wide dynamic range are important. For many applications they are not. I think this ADC design will work very well. I\'m interested in characterizing the performance to see just how well they can work.

--

Rick C.

-- Get 1,000 miles of free Supercharging
-- Tesla referral code - https://ts.la/richard11209

 

[server]

Rick C <gnuarm.deletethisbit@gmail.com> wrote:

On Thursday, November 26, 2020 at 5:37:15 PM UTC-5, anti...@math.uni.wroc.pl wrote:
Rickster C <gnuarm.del...@gmail.com> wrote:
I\'ve been messing with this for a bit and the ultimate limitation seems to me to not be the digital noise in the FPGA, but rather the imbalance in the edge rise/fall times and/or propagation delays.
Well, \"ultimate\" circuits usually depend on compensation and
calibration. So limits are due to inability to compensate
(or remove via calibration) error. For example short
term drifts may be problematic. In current times it
seems that \"ultimate\" circuits usualy will be IC,
because:
- some good elements are available only as parts of IC
- lower parasitics
- matching of elements
- trimming on IC seem to be significantly less expensive
than trimming of discrete circuits

Some of these issues are mitigated by the circuit design. The C is not relevant since the time constant does not factor into the accuracy of the unit, only that it does not change, so no microphonic ceramic caps. The value of R is also not a factor in the accuracy of the unit, only that it does not change which relates to the relative contributions of the high and low resistance of the driver. This is mitigated by the relative value of the circuit resistance swamping out small variations in driving resistance. However, for a given time constant a larger resistor uses a smaller capacitor which accentuates imbalances in charge injection.


However, it seems that you have concrete circuit in mind
with requiraments that are very far from \"ultimate\".

Not sure what that means really. The requirements are for resolution to 14 bits. With a 10 bit converter the resolution of the signal does not give adequate resolution in the output as a square root function is involved. The current test board has an amplifier to allow the low range to be measured with higher resolution. Measuring the full range with more resolution will eliminate the need for additional amplifiers and ADC circuits. The time window for making the measurement and the clock used provides 17.3 bits of count. No reason to toss any of those bits. The accuracy of the measurements is 2.5%. But accuracy is not resolution and the requirements do not need to match up.


The digital noise in the FPGA is going to be mostly in the core. The I/Os are the part that matter to the analog portion of the ADC and they have separate Vcco from the core and also one another. I\'ve been planning to dedicate a bank to the ADCs. But the input signals have a 5 volt range and will require a 3.3 Vcco that is ratiometric to the 5 volt supply. It seemed simpler to add a 5 volt level shifter and let that be powered by the sensor 5 volt rail.

So now I\'m looking for the right buffer device and I\'m starting to realize the limitation is the symmetry in the rise/fall times and the propagation delays of the two edges. Buffers are not so good with this having delays of single digit ns, but also lack of symmetry of single digit ns. With 30 ns pulses, that would add up. I thought analog switches might be better, but they are worse with unbalanced switching times being hard to get into the low single digit ns. Many of the parts I find a LVC which require 3.5 volt inputs when powered from 5V.

Anyone know of parts that would be good for this? Would it make sense to run through two buffers at least conceptually balancing the rise/fall times and prop delays? But then the delays start to add up, but that probably doesn\'t matter as much.
In other post you mention 74ACT244. AFAIK HC type gate were used
as switches in reasonably precise circuits. OTOH a lot depends
on specific details of your circuit. In post in comp.dsp you
gave some details of your circit (I assume you mean the same
circuit here). To say the truth, I would describe it not as
delta-sigma but as multiple slope convertor.

Not sure why you say that. A slope converter measures the time of charging or discharging a capacitor with no feedback, just a threshold to obtain the measurement. Here the circuit essentially is using a feedback loop to balance the currents feeding the capacitor to maintain a constant voltage. This feedback creates a density modulated pulse stream. That\'s nothing like a slope converter.

Well, apparently you do not use any fancy sigma-delta stuff.
I prefar saying about multiple slope convertor, because there
is wide family of convertors sharing the same basic principle,
but differing in details. Relevant here is convertor having
comparator with hysteresis, so there are two thresholds.
In classic dual slope one threshold is replaced by timed
charging of integrating capacitor from reference voltage,
but this from my point of view does not change too much.
More relevant is difference between upper and lower threshold.
In dual slope it is relativly large. In multiple slope
difference between thresholds may be lowered. IIUC you
plan single threshold, so that exact switching times
are dictated by noise and hysteresis is replaced by
synchronized switching (only when clock changes). This
also forced relatively high switching frequency (of the
same order as digital clock). One point of my analysis
below is that lower switching frequency reduces error
due to imperfect switching. Hysteresis allows lower
switching frequency keeping high digital clock and
consequently also high resolution.

You have
integrating capacitor that is connected via resitor to input voltage,
via switch and resitor to either ground or positive supply
and to comparator that compares voltage on capacitor with
rererence voltage. In first order approximation voltage
on capacitor is triangular and we have equality:

V_0/R_0 = MV_1/R_1 + NV_2/R_2 + n(C_1 + C_2)

where V_0 = V_in - V_a is difference between input voltage
and average voltage on the capacitor, V_a is average voltage
on the capacitor, V_1 = V_cc - V_a is difference between
supply voltage and average voltage on the capacitor,
V_2 = -V_a, M is fraction of time when switch is
connected to V_cc, R_1 is sum of resitor and switch
resistance, N is fraction of time when switch is
connected to ground, R_2 is sum of resitor and switch
resistance, n is switching frequency, C_1 is is extra
charge transferred during switching up, C_2 is
extra charge transferred during switching down.
With ideal switches R_1 = R_2 is just resitistance
between integrating capacitor and the switch and
C_1 = C_2 = 0. With non-ideal idealy balanced switch
C_1 = -C_2 so switching error vanishes and switch
resistance just changes scale factor. With unbalanced
switch we still can try to calibrate it out: other
terms are linear so three point calibation can
null switching error term. CMOS chips have switching
characteristics that depend on temperature, so there
are limits to calibration, but one can do better
than magnitide of switching errors would suggest.

Concerning symmetry of switches, I see nothing in
ACT244 datasheet that would claim symmetry. Bounds
are symmetric, but are quite wide so highly
asymetric chip will still stay withing datasheet
bound.

No, there is no spec on balance, but the symmetrical specifications would indicate the design is symmetrical. No reason to expect wide differences. It\'s a good as it will be unless devices are used with balance specs and I found none that would be appropriate. I looked at using analog switches to multiplex voltages and found excessive shoot through. Seems many are designed to make before break. Also the switching times are slow compared to my clock. I\'m giving thought to slowing the clock rate to minimize the injection potential since we have more than adequate resolution.

Well, specs for cheap analog multiplexers say that switches are
balanced +- 10%. I see no reason to expect better balance from
digital gates. And I see reasons that balance may be much worse.

Anyway, holes have lower mobility, so p-chanel MOSFET must be
bigger than n-chanel to have comparable on resistance. But
then capacitances in p-MOSFET will be larger which affects
switching time. So actual design _must_ be asymetric and
designers must decide how to balance it.

I have no equipment to measure propagation
delay, but I measured switch resistance for some
chips (both from chinese selers, so possibly fake).
HC00 was reasonably symmetric, in HC04 lower
switch had 3 time lower resistance than high switch.
As I wrote, they may be fake, but resistance was
well within datasheet bounds. BTW: I looked at
HC chips because they are faster and have
lower resistance than cheap analog switches.
And I hoped for better symmetry in HC than
in ACT.

Yes, I found analog switches to be inordinately slow as well. The HC devices are also not very fast and it would be required to use the HCT devices to maintain 3V input compatibility. The ACT was the device with the best spec in the \'T\' category I could find. There are no shortages of \"categories\" when it comes to logic families.

Well, I understand that you may prefer ACT. Simply, I had
different constraints.

More generaly, charge balance principle (like
in Pease or Wiliams voltage to frequency convertors)
may give better accuracy, because charge is
determined by reference voltage and charging
capactor and depends very weakly on switch
parameters. Of course, drawback is that
you would need two good capacitors.

It\'s also a lot of circuit. The point is to minimize the devices needed and working with the FPGA digital domain primarily. I\'m making one concession of using an external buffer chip for the 1-bit DACs. The FPGA comparator inputs are being used however because it is too much to add a comparator for every ADC in the design. Anything more than the buffer and I might as well use an ADC chip.

I think a lot of people are intimidated by using something that is new to them and no one they know is using it. The various reports focus on the use for applications where high SNR and wide dynamic range are important. For many applications they are not. I think this ADC design will work very well. I\'m interested in characterizing the performance to see just how well they can work.

--
Waldek Hebisch

 

[Rick C]

On Wednesday, December 2, 2020 at 8:43:43 PM UTC-5, anti...@math.uni.wroc.pl wrote:

Rick C <gnuarm.del...@gmail.com> wrote:
On Thursday, November 26, 2020 at 5:37:15 PM UTC-5, anti...@math.uni.wroc.pl wrote:
Rickster C <gnuarm.del...@gmail.com> wrote:
I\'ve been messing with this for a bit and the ultimate limitation seems to me to not be the digital noise in the FPGA, but rather the imbalance in the edge rise/fall times and/or propagation delays.
Well, \"ultimate\" circuits usually depend on compensation and
calibration. So limits are due to inability to compensate
(or remove via calibration) error. For example short
term drifts may be problematic. In current times it
seems that \"ultimate\" circuits usualy will be IC,
because:
- some good elements are available only as parts of IC
- lower parasitics
- matching of elements
- trimming on IC seem to be significantly less expensive
than trimming of discrete circuits

Some of these issues are mitigated by the circuit design. The C is not relevant since the time constant does not factor into the accuracy of the unit, only that it does not change, so no microphonic ceramic caps. The value of R is also not a factor in the accuracy of the unit, only that it does not change which relates to the relative contributions of the high and low resistance of the driver. This is mitigated by the relative value of the circuit resistance swamping out small variations in driving resistance. However, for a given time constant a larger resistor uses a smaller capacitor which accentuates imbalances in charge injection.


However, it seems that you have concrete circuit in mind
with requiraments that are very far from \"ultimate\".

Not sure what that means really. The requirements are for resolution to 14 bits. With a 10 bit converter the resolution of the signal does not give adequate resolution in the output as a square root function is involved. The current test board has an amplifier to allow the low range to be measured with higher resolution. Measuring the full range with more resolution will eliminate the need for additional amplifiers and ADC circuits. The time window for making the measurement and the clock used provides 17.3 bits of count. No reason to toss any of those bits. The accuracy of the measurements is 2.5%. But accuracy is not resolution and the requirements do not need to match up.


The digital noise in the FPGA is going to be mostly in the core. The I/Os are the part that matter to the analog portion of the ADC and they have separate Vcco from the core and also one another. I\'ve been planning to dedicate a bank to the ADCs. But the input signals have a 5 volt range and will require a 3.3 Vcco that is ratiometric to the 5 volt supply. It seemed simpler to add a 5 volt level shifter and let that be powered by the sensor 5 volt rail.

So now I\'m looking for the right buffer device and I\'m starting to realize the limitation is the symmetry in the rise/fall times and the propagation delays of the two edges. Buffers are not so good with this having delays of single digit ns, but also lack of symmetry of single digit ns. With 30 ns pulses, that would add up. I thought analog switches might be better, but they are worse with unbalanced switching times being hard to get into the low single digit ns. Many of the parts I find a LVC which require 3.5 volt inputs when powered from 5V.

Anyone know of parts that would be good for this? Would it make sense to run through two buffers at least conceptually balancing the rise/fall times and prop delays? But then the delays start to add up, but that probably doesn\'t matter as much.
In other post you mention 74ACT244. AFAIK HC type gate were used
as switches in reasonably precise circuits. OTOH a lot depends
on specific details of your circuit. In post in comp.dsp you
gave some details of your circit (I assume you mean the same
circuit here). To say the truth, I would describe it not as
delta-sigma but as multiple slope convertor.

Not sure why you say that. A slope converter measures the time of charging or discharging a capacitor with no feedback, just a threshold to obtain the measurement. Here the circuit essentially is using a feedback loop to balance the currents feeding the capacitor to maintain a constant voltage. This feedback creates a density modulated pulse stream. That\'s nothing like a slope converter.
Well, apparently you do not use any fancy sigma-delta stuff.

Not sure of the meaning of either \"fancy\" or \"stuff\". The circuit is a sigma-delta converter as the analog components with the differential receiver form the modulator. Not sure why you seem to be saying it\'s not.

I prefar saying about multiple slope convertor, because there
is wide family of convertors sharing the same basic principle,
but differing in details. Relevant here is convertor having
comparator with hysteresis, so there are two thresholds.
In classic dual slope one threshold is replaced by timed
charging of integrating capacitor from reference voltage,
but this from my point of view does not change too much.
More relevant is difference between upper and lower threshold.
In dual slope it is relativly large. In multiple slope
difference between thresholds may be lowered. IIUC you
plan single threshold, so that exact switching times
are dictated by noise and hysteresis is replaced by
synchronized switching (only when clock changes). This
also forced relatively high switching frequency (of the
same order as digital clock). One point of my analysis
below is that lower switching frequency reduces error
due to imperfect switching. Hysteresis allows lower
switching frequency keeping high digital clock and
consequently also high resolution.

Yes, it has occurred to me that a lower input sampling rate would minimize *some* of the driver errors but until the extent is known, there is no way to obtain a trade off with the loss of resolution as the switching rate decreases. Since this is controlled by the digital sample rate it can be adjusted once the unit is ready for testing.

The possible errors are imbalances causing offset errors, gain errors and gamma errors (non-linearity). Offset errors will be calibrated out when sensor errors are calibrated. Most sensors will not require gain calibration, but I don\'t expect significant gain errors. They would mostly be from unequal drive strength which will be minimized by the large size of the circuit resistors.

There are non-linear errors which can arise from charge injection. This will be a bias that is dependent on switching frequency of the feedback signal. Likewise unequal delay times will also introduce switching rate dependent errors, which I attempted to minimize in the driver component selection.. The frequency of the feedback signal is highest at the mid point falling off as the input rises or falls. This will produce a curve in the response. We can measure this. If the impact is too great the input sampling rate will need to be adjusted to reduce it. This may end up being the ultimate limit to the resolution of the converter for a given output sample rate.

You have
integrating capacitor that is connected via resitor to input voltage,
via switch and resitor to either ground or positive supply
and to comparator that compares voltage on capacitor with
rererence voltage. In first order approximation voltage
on capacitor is triangular and we have equality:

V_0/R_0 = MV_1/R_1 + NV_2/R_2 + n(C_1 + C_2)

where V_0 = V_in - V_a is difference between input voltage
and average voltage on the capacitor, V_a is average voltage
on the capacitor, V_1 = V_cc - V_a is difference between
supply voltage and average voltage on the capacitor,
V_2 = -V_a, M is fraction of time when switch is
connected to V_cc, R_1 is sum of resitor and switch
resistance, N is fraction of time when switch is
connected to ground, R_2 is sum of resitor and switch
resistance, n is switching frequency, C_1 is is extra
charge transferred during switching up, C_2 is
extra charge transferred during switching down.
With ideal switches R_1 = R_2 is just resitistance
between integrating capacitor and the switch and
C_1 = C_2 = 0. With non-ideal idealy balanced switch
C_1 = -C_2 so switching error vanishes and switch
resistance just changes scale factor. With unbalanced
switch we still can try to calibrate it out: other
terms are linear so three point calibation can
null switching error term. CMOS chips have switching
characteristics that depend on temperature, so there
are limits to calibration, but one can do better
than magnitide of switching errors would suggest.

Concerning symmetry of switches, I see nothing in
ACT244 datasheet that would claim symmetry. Bounds
are symmetric, but are quite wide so highly
asymetric chip will still stay withing datasheet
bound.

No, there is no spec on balance, but the symmetrical specifications would indicate the design is symmetrical. No reason to expect wide differences.. It\'s a good as it will be unless devices are used with balance specs and I found none that would be appropriate. I looked at using analog switches to multiplex voltages and found excessive shoot through. Seems many are designed to make before break. Also the switching times are slow compared to my clock. I\'m giving thought to slowing the clock rate to minimize the injection potential since we have more than adequate resolution.
Well, specs for cheap analog multiplexers say that switches are
balanced +- 10%. I see no reason to expect better balance from
digital gates. And I see reasons that balance may be much worse.

Anyway, holes have lower mobility, so p-chanel MOSFET must be
bigger than n-chanel to have comparable on resistance. But
then capacitances in p-MOSFET will be larger which affects
switching time. So actual design _must_ be asymetric and
designers must decide how to balance it.
I have no equipment to measure propagation
delay, but I measured switch resistance for some
chips (both from chinese selers, so possibly fake).
HC00 was reasonably symmetric, in HC04 lower
switch had 3 time lower resistance than high switch.
As I wrote, they may be fake, but resistance was
well within datasheet bounds. BTW: I looked at
HC chips because they are faster and have
lower resistance than cheap analog switches.
And I hoped for better symmetry in HC than
in ACT.

Yes, I found analog switches to be inordinately slow as well. The HC devices are also not very fast and it would be required to use the HCT devices to maintain 3V input compatibility. The ACT was the device with the best spec in the \'T\' category I could find. There are no shortages of \"categories\" when it comes to logic families.
Well, I understand that you may prefer ACT. Simply, I had
different constraints.
More generaly, charge balance principle (like
in Pease or Wiliams voltage to frequency convertors)
may give better accuracy, because charge is
determined by reference voltage and charging
capactor and depends very weakly on switch
parameters. Of course, drawback is that
you would need two good capacitors.

It\'s also a lot of circuit. The point is to minimize the devices needed and working with the FPGA digital domain primarily. I\'m making one concession of using an external buffer chip for the 1-bit DACs. The FPGA comparator inputs are being used however because it is too much to add a comparator for every ADC in the design. Anything more than the buffer and I might as well use an ADC chip.

I think a lot of people are intimidated by using something that is new to them and no one they know is using it. The various reports focus on the use for applications where high SNR and wide dynamic range are important. For many applications they are not. I think this ADC design will work very well. I\'m interested in characterizing the performance to see just how well they can work.

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Rick C.

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