Delta-Sigma in an FPGA

R

Rob Gaddi

Guest
Hey all --

So I've got yet another project making me say "Gosh it'd be nice to be
able to implement a DAC/ADC directly in the FPGA." And so I looked
around and found all the same white papers I always find wherein a
first-order delta-sigma modulated ADC or DAC is implemented using only
an FPGA and an RC filter.

I've done the DAC one before, but only in closed loop situations where
the actual accuracy doesn't matter much. Has anyone actually tried
doing either of these in a real quantitative sense and gotten a feel for
what sorts of results can be accomplished?

Offhand, it seems like if you managed 12 bits it'd be a miracle. Even
if you stabilized the power supply voltages (and had zero ground bounce
induced by the rest of the logic), it seems like you'd need rise/fall
symmetry into the femtoseconds on the digital outputs in order to not
shoot your linearity.

--
Rob Gaddi, Highland Technology
Email address is currently out of order
 
On 06/28/2011 09:34 AM, Rob Gaddi wrote:
Hey all --

So I've got yet another project making me say "Gosh it'd be nice to be
able to implement a DAC/ADC directly in the FPGA." And so I looked
around and found all the same white papers I always find wherein a
first-order delta-sigma modulated ADC or DAC is implemented using only
an FPGA and an RC filter.

I've done the DAC one before, but only in closed loop situations where
the actual accuracy doesn't matter much. Has anyone actually tried doing
either of these in a real quantitative sense and gotten a feel for what
sorts of results can be accomplished?

Offhand, it seems like if you managed 12 bits it'd be a miracle. Even if
you stabilized the power supply voltages (and had zero ground bounce
induced by the rest of the logic), it seems like you'd need rise/fall
symmetry into the femtoseconds on the digital outputs in order to not
shoot your linearity.
Click to expand...
I've done this exactly once -- I implemented a DAC that fed the
ever-hi-fi LM386 (or maybe it was an LM358 and a couple of transistors)
and a little speaker out of my junk box. I needed it to listen in on
digital phone signals that I was decoding, and I have to say, the dial
tone was unambiguous every time.

I suspect that if you wanted to do this for real it would be essential
to use an external part for the 1-bit DAC element. Up to some point you
could probably get away with a single-gate 74xx04 -- something like an
AHC or similar way-fast, way-high-drive family, operating into a fairly
high impedance, should give you decent symmetry.

Power that part off of its very own, very quiet supply, be very careful
with grounds, and you may be able to do astonishing things. I think 12
bits would come easily, and I'm willing to bet that 16 bits wouldn't be
at all unachievable. In fact, you may even be able to do something
perverted like compensating for the analog asymmetry in digital-land,
and push the thing up to 20 bits -- assuming that all the surrounding
circuitry were good for that.

I do think that you'd want to go to at least a 2nd-order sigma-delta,
however.

Patent the approach when you're done, and sell the IP on Xilinx's and
Altera's IP store.

--

Tim Wescott
Wescott Design Services
http://www.wescottdesign.com

Do you need to implement control loops in software?
"Applied Control Theory for Embedded Systems" was written for you.
See details at http://www.wescottdesign.com/actfes/actfes.html
 
"Tim Wescott" <tim@seemywebsite.com> wrote in message
news:OrqdnZgJPa5oi5fTnZ2dnUVZ_sednZ2d@web-ster.com...
On 06/28/2011 09:34 AM, Rob Gaddi wrote:
Hey all --

So I've got yet another project making me say "Gosh it'd be nice to be
able to implement a DAC/ADC directly in the FPGA." And so I looked
around and found all the same white papers I always find wherein a
first-order delta-sigma modulated ADC or DAC is implemented using only
an FPGA and an RC filter.

I've done the DAC one before, but only in closed loop situations where
the actual accuracy doesn't matter much. Has anyone actually tried doing
either of these in a real quantitative sense and gotten a feel for what
sorts of results can be accomplished?

Offhand, it seems like if you managed 12 bits it'd be a miracle. Even if
you stabilized the power supply voltages (and had zero ground bounce
induced by the rest of the logic), it seems like you'd need rise/fall
symmetry into the femtoseconds on the digital outputs in order to not
shoot your linearity.

I've done this exactly once -- I implemented a DAC that fed the ever-hi-fi
LM386 (or maybe it was an LM358 and a couple of transistors) and a little
speaker out of my junk box. I needed it to listen in on digital phone
signals that I was decoding, and I have to say, the dial tone was
unambiguous every time.

I suspect that if you wanted to do this for real it would be essential to
use an external part for the 1-bit DAC element. Up to some point you
could probably get away with a single-gate 74xx04 -- something like an AHC
or similar way-fast, way-high-drive family, operating into a fairly high
impedance, should give you decent symmetry.
Click to expand...
Or an LVDS line receiver

Power that part off of its very own, very quiet supply,
Click to expand...
Yep

be very careful with grounds, and you may be able to do astonishing things.
Click to expand...
LVDS helps here
 
On Tue, 28 Jun 2011 21:18:07 +0100, Andrew Holme wrote:

"Tim Wescott" <tim@seemywebsite.com> wrote in message
news:OrqdnZgJPa5oi5fTnZ2dnUVZ_sednZ2d@web-ster.com...
On 06/28/2011 09:34 AM, Rob Gaddi wrote:
Hey all --

So I've got yet another project making me say "Gosh it'd be nice to be
able to implement a DAC/ADC directly in the FPGA." And so I looked
around and found all the same white papers I always find wherein a
first-order delta-sigma modulated ADC or DAC is implemented using only
an FPGA and an RC filter.

I've done the DAC one before, but only in closed loop situations where
the actual accuracy doesn't matter much. Has anyone actually tried
doing either of these in a real quantitative sense and gotten a feel
for what sorts of results can be accomplished?

Offhand, it seems like if you managed 12 bits it'd be a miracle. Even
if you stabilized the power supply voltages (and had zero ground
bounce induced by the rest of the logic), it seems like you'd need
rise/fall symmetry into the femtoseconds on the digital outputs in
order to not shoot your linearity.

I've done this exactly once -- I implemented a DAC that fed the
ever-hi-fi LM386 (or maybe it was an LM358 and a couple of transistors)
and a little speaker out of my junk box. I needed it to listen in on
digital phone signals that I was decoding, and I have to say, the dial
tone was unambiguous every time.

I suspect that if you wanted to do this for real it would be essential
to use an external part for the 1-bit DAC element. Up to some point
you could probably get away with a single-gate 74xx04 -- something like
an AHC or similar way-fast, way-high-drive family, operating into a
fairly high impedance, should give you decent symmetry.

Or an LVDS line receiver

Power that part off of its very own, very quiet supply,

Yep

be very careful with grounds, and you may be able to do astonishing
things.

LVDS helps here
Click to expand...
Wow -- I hadn't even thought about clock jitter. I should have, but I
didn't.

I suppose if you _really_ wanted to do a hot-stuff job you'd take the
modulator output from the FPGA and regenerate it with a way-clean clock.
You'll end up with delay in your loop, but lose some noise.

You'd have to sit back and do some math to figure out what sort of
performance could be hoped for from an any-old-which-way implementation.

--
Tim Wescott
Control system and signal processing consulting
www.wescottdesign.com
 
On 6/28/2011 10:50 PM, Tim wrote:
On Tue, 28 Jun 2011 21:18:07 +0100, Andrew Holme wrote:

"Tim Wescott"<tim@seemywebsite.com> wrote in message
news:OrqdnZgJPa5oi5fTnZ2dnUVZ_sednZ2d@web-ster.com...
On 06/28/2011 09:34 AM, Rob Gaddi wrote:
Hey all --

So I've got yet another project making me say "Gosh it'd be nice to be
able to implement a DAC/ADC directly in the FPGA." And so I looked
around and found all the same white papers I always find wherein a
first-order delta-sigma modulated ADC or DAC is implemented using only
an FPGA and an RC filter.

I've done the DAC one before, but only in closed loop situations where
the actual accuracy doesn't matter much. Has anyone actually tried
doing either of these in a real quantitative sense and gotten a feel
for what sorts of results can be accomplished?

Offhand, it seems like if you managed 12 bits it'd be a miracle. Even
if you stabilized the power supply voltages (and had zero ground
bounce induced by the rest of the logic), it seems like you'd need
rise/fall symmetry into the femtoseconds on the digital outputs in
order to not shoot your linearity.

I've done this exactly once -- I implemented a DAC that fed the
ever-hi-fi LM386 (or maybe it was an LM358 and a couple of transistors)
and a little speaker out of my junk box. I needed it to listen in on
digital phone signals that I was decoding, and I have to say, the dial
tone was unambiguous every time.

I suspect that if you wanted to do this for real it would be essential
to use an external part for the 1-bit DAC element. Up to some point
you could probably get away with a single-gate 74xx04 -- something like
an AHC or similar way-fast, way-high-drive family, operating into a
fairly high impedance, should give you decent symmetry.

Or an LVDS line receiver

Power that part off of its very own, very quiet supply,

Yep

be very careful with grounds, and you may be able to do astonishing
things.

LVDS helps here

Wow -- I hadn't even thought about clock jitter. I should have, but I
didn't.

I suppose if you _really_ wanted to do a hot-stuff job you'd take the
modulator output from the FPGA and regenerate it with a way-clean clock.
You'll end up with delay in your loop, but lose some noise.

You'd have to sit back and do some math to figure out what sort of
performance could be hoped for from an any-old-which-way implementation.
Click to expand...
And of course, as you start adding more external parts to the solution,
the advantages in board space and cost over just buying a chip vanish.

--
Rob Gaddi, Highland Technology
Email address is currently out of order
 
On 06/29/2011 09:18 AM, Rob Gaddi wrote:
On 6/28/2011 10:50 PM, Tim wrote:
On Tue, 28 Jun 2011 21:18:07 +0100, Andrew Holme wrote:

"Tim Wescott"<tim@seemywebsite.com> wrote in message
news:OrqdnZgJPa5oi5fTnZ2dnUVZ_sednZ2d@web-ster.com...
On 06/28/2011 09:34 AM, Rob Gaddi wrote:
Hey all --

So I've got yet another project making me say "Gosh it'd be nice to be
able to implement a DAC/ADC directly in the FPGA." And so I looked
around and found all the same white papers I always find wherein a
first-order delta-sigma modulated ADC or DAC is implemented using only
an FPGA and an RC filter.

I've done the DAC one before, but only in closed loop situations where
the actual accuracy doesn't matter much. Has anyone actually tried
doing either of these in a real quantitative sense and gotten a feel
for what sorts of results can be accomplished?

Offhand, it seems like if you managed 12 bits it'd be a miracle. Even
if you stabilized the power supply voltages (and had zero ground
bounce induced by the rest of the logic), it seems like you'd need
rise/fall symmetry into the femtoseconds on the digital outputs in
order to not shoot your linearity.

I've done this exactly once -- I implemented a DAC that fed the
ever-hi-fi LM386 (or maybe it was an LM358 and a couple of transistors)
and a little speaker out of my junk box. I needed it to listen in on
digital phone signals that I was decoding, and I have to say, the dial
tone was unambiguous every time.

I suspect that if you wanted to do this for real it would be essential
to use an external part for the 1-bit DAC element. Up to some point
you could probably get away with a single-gate 74xx04 -- something like
an AHC or similar way-fast, way-high-drive family, operating into a
fairly high impedance, should give you decent symmetry.

Or an LVDS line receiver

Power that part off of its very own, very quiet supply,

Yep

be very careful with grounds, and you may be able to do astonishing
things.

LVDS helps here

Wow -- I hadn't even thought about clock jitter. I should have, but I
didn't.

I suppose if you _really_ wanted to do a hot-stuff job you'd take the
modulator output from the FPGA and regenerate it with a way-clean clock.
You'll end up with delay in your loop, but lose some noise.

You'd have to sit back and do some math to figure out what sort of
performance could be hoped for from an any-old-which-way implementation.


And of course, as you start adding more external parts to the solution,
the advantages in board space and cost over just buying a chip vanish.
Click to expand...
True. But when you get right down to it, for an ADC just implementing
the necessary op-amp integrator and comparator is going to rival an
external ADC chip.

So maybe the thing to do is to figure out the best DAC that you can do
with FPGA only, and leave it at that...

--

Tim Wescott
Wescott Design Services
http://www.wescottdesign.com

Do you need to implement control loops in software?
"Applied Control Theory for Embedded Systems" was written for you.
See details at http://www.wescottdesign.com/actfes/actfes.html
 
Rob Gaddi wrote:

Offhand, it seems like if you managed 12 bits it'd be a miracle. Even
if you stabilized the power supply voltages (and had zero ground bounce
induced by the rest of the logic), it seems like you'd need rise/fall
symmetry into the femtoseconds on the digital outputs in order to not
shoot your linearity.
Click to expand...
There is a paper which states that they can do 24 bit:

http://www.cse.cuhk.edu.hk/~phwl/mt/public/archives/papers/dac_fpt03.pdf

But I didn't found a description of the output stage. They measured -112
dB THD+N, but I don't think with all the noise on the supply voltages of
a FPGA that they drive a RC filter directly.

--
Frank Buss, http://www.frank-buss.de
piano and more: http://www.youtube.com/user/frankbuss
 
On 7/2/2011 11:15 AM, Frank Buss wrote:
Rob Gaddi wrote:

Offhand, it seems like if you managed 12 bits it'd be a miracle. Even
if you stabilized the power supply voltages (and had zero ground bounce
induced by the rest of the logic), it seems like you'd need rise/fall
symmetry into the femtoseconds on the digital outputs in order to not
shoot your linearity.

There is a paper which states that they can do 24 bit:

http://www.cse.cuhk.edu.hk/~phwl/mt/public/archives/papers/dac_fpt03.pdf

But I didn't found a description of the output stage. They measured -112
dB THD+N, but I don't think with all the noise on the supply voltages of
a FPGA that they drive a RC filter directly.
Click to expand...
God bless academics:

"In order to debug the system in a noise free environment, we used an
Agilent 16702B Logic analysis system to measure the output different
bit-width and order settings. The state mode sampling method is chosen
for synchronous sampling clocked by the FPGA board itself so that the
exact output of the DAC can be captured by the logic analyzer."

i.e. Measurements were taken to confirm that we get a stream of ones and
zeros that we can assume to be perfect rectangles framed by a perfect
clock. One day, we hope to use this to generate an analog waveform that
we expect to have characteristics.

Can't imagine why I decided not to go for that PhD.

--
Rob Gaddi, Highland Technology
Email address is currently out of order
 
On Jul 6, 5:09 am, Rob Gaddi <rga...@technologyhighland.com> wrote:
God bless academics:
Click to expand...
Yes, I love the -250dB noise floors on the plots, which (of course)
are simulated.

and real measurements, are entirely optional, 'we'll get to that
later' !!

["An Audio Precision System Two Cascade audio analyzer with -112dB THD
+N for a 20kHz input will be used to further verify the system and
results will be presented at the conference."]

- but yes, in the real world, you can build 24b calibration DACs,
using an external element for the 1 bit DAC.
 
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