Delta delay in vhdl

[priya]

Hi all?

some one explain me what is delta delay in VHDL?



regds,
priya

 

[Mike Treseler]

priya wrote:

some one explain me what is delta delay in VHDL?

http://www.google.com/search?q=vhdl+delta+delay+provide+minimum

 

[Harry Athanassiadis]

is the simulation cycle
Harry A


"priya" <priya11.karthik@gmail.com> wrote in message
news:1129980111.445993.84500@f14g2000cwb.googlegroups.com...

Hi all?

some one explain me what is delta delay in VHDL?



regds,
priya

 

[anupam]

hi,
Every signal inside the process is assigned value after a delay callled
"delta delay".
Inside a process variabes are assigned values then and there while the
new values to the signals are updated only when the whole process is
scanned.
This means any updated value on the signal is not considered as new
value for the rest of the lines of code at a particular clk cycle.
eg:lets say a has '0' initially
process(clk,reset)
a<= '1';
b<=a;
end process;
At first clock though code is executed sequentially the new value(i.e,
1) of a is not assigned to b.
So all the values are assigned after delta delay so when the simulator
reaches b<=a statement the value of a is still 0 since detla delay is
not elapsed.

regards,
Anupam Jain