delays: inertial delays vs. transport delays

[Neil Zanella]

Hello,

I have some issues with delays which I would appreciate very much if
someone could please clarify for me, as they are not clear to me right
now. I would like to know what the difference between an inertial delay
and a transport delay is and why VHDL would need to have these two
distinct types of delay. Also, it seems to me that specifying delays in
VHDL designs can only serve the purose of simulation since the delays
inherent in the physical hardware cannot, as far as I know, be
controlled with software: they certainly cannot be made smaller
than what they are, but I'm not sure if you could use a flip-flop
to make them longer if necessary. In any case, I thought that the
delays need not be specified since the simulation software usually
allows the user to select the target hardware, and knows what the
delays inherent in the selected target hardware are supposed to be.

So are delays used only for simulation purposes, and why would they
need to be specified in the VHDL file instead of being known by the
simulation software based on the physical characteristics of the
target FPGA or CPLD.

Thank you for your clarifications,

Neil

 

[Andrew Reynolds]

Neil Zanella wrote:

Hello,

I have some issues with delays which I would appreciate very much if
someone could please clarify for me, as they are not clear to me right
now. I would like to know what the difference between an inertial delay
and a transport delay is and why VHDL would need to have these two
distinct types of delay.

Inertial delay is the time it takes for a signal to change its value.
This is usually representative of capacitance.

Transport delay is the time it takes a signal to travel across a wire.
It physically takes time for electrons to move through any conductive
material.

Also, it seems to me that specifying delays in
VHDL designs can only serve the purose of simulation since the delays
inherent in the physical hardware cannot, as far as I know, be
controlled with software: they certainly cannot be made smaller
than what they are, but I'm not sure if you could use a flip-flop
to make them longer if necessary. In any case, I thought that the
delays need not be specified since the simulation software usually
allows the user to select the target hardware, and knows what the
delays inherent in the selected target hardware are supposed to be.

Delays are usually used for behavioral models to better represent
signalling at their external interface.

So are delays used only for simulation purposes, and why would they
need to be specified in the VHDL file instead of being known by the
simulation software based on the physical characteristics of the
target FPGA or CPLD.

Yes. Delays are usually used for simulation. They can represent the
physical design using SDF (Standard Delay Format) back-annotation in the
simualator. VITAL (VHDL Initiative Towards ASIC Librarues) can be used
to develop libraries that represent foundary libraries and includes
delays that are both intrinsic and back-annotated from the Physical
Design tools using SDF.

Thank you for your clarifications,

Neil

 

[Niv]

Inertial delay is the time it takes for a signal to change its value.
This is usually representative of capacitance.

Transport delay is the time it takes a signal to travel across a wire.
It physically takes time for electrons to move through any conductive
material.

If you model an inertial delay of, say 20 ns, and then put a pulse of, say,
10ns, through the model, it will be "swallowed" and will not appear at the
output.

Conversely, if you model a transport delay of, say 20 ns, and then put a
pulse of, say, 10ns, through the model, it will be merely delayed by the 20
ns, and will appear.

Anyway, that's what I've found (I think).
Niv.