Delay with buffers

[ratep2001]

I have the following problem: I want to implement large delays
(50-100ns) on some signals in my VHDL code and fit them into a CPLD,
and for that purpose I use chained buffers. However, I found that
although I use the attributes for preservation of nodes/signals
("syn_keep" for Synplify and "opt" for the optimizer), I cannot
preserve more than one single buffer.

For example, in the code below I want to fit 7 buffers between the
input and the output signal. However, I don't get 7 chained buffers in
my pre-fit equations, but just a single buffer buf7 on my input signal.
So I end up with just a few nanoseconds of delay, which is far from
sufficient.

Is there any elegant way to create more than one buffer, and preserve
it from collapsing? I can use either Synplify - Synplicity or Leonardo
Spectrum - Menthor Graphics.

Best regards,
Petar

--------------------------------------
Example VHDL code

library ieee;
use ieee.std_logic_1164.all;

entity delay_block is
port
(
in_signal: IN STD_LOGIC;
out_signal: OUT STD_LOGIC
);

end;

architecture delay_block_arch of delay_block is

signal buf1, buf2, buf3, buf4, buf5, buf6, buf7: STD_LOGIC;

attribute syn_keep: integer;
attribute syn_keep of buf1, buf2, buf3, buf4, buf5, buf6, buf7: signal
is 1;

attribute OPT: string;
attribute OPT of buf1, buf2, buf3, buf4, buf5, buf6, buf7: signal is
"KEEP";

begin
buf1 <= in_signal;
buf2 <= buf1;
buf3 <= buf2;
buf4 <= buf3;
buf5 <= buf4;
buf6 <= buf5;
buf7 <= buf6;
out_signal <= buf7;

end delay_block_arch;


--
ratep2001www.totallychips.com - VHDL, Verilog & General Hardware Design discussion Forum

 

[Mike Treseler]

ratep2001 wrote:

I have the following problem: I want to implement large delays
(50-100ns) on some signals in my VHDL code and fit them into a CPLD,
and for that purpose I use chained buffers. However, I found that
although I use the attributes for preservation of nodes/signals
("syn_keep" for Synplify and "opt" for the optimizer), I cannot
preserve more than one single buffer.

Consider using a shift register.

-- Mike Treseler

 

[Peter Hermansson]

Is there any elegant way to create more than one buffer, and preserve
it from collapsing? I can use either Synplify - Synplicity or Leonardo
Spectrum - Menthor Graphics.

Best regards,
Petar

Hi,

Using buffers as delay elements is never a good idea in programmable
logic.
They may (as you have already seen) be optimized away and the delay is
very unpredictable, varying over temperature, voltage and between
batches.
A better idea is to use synchronous logic to create delays (as Mike
Treseler suggest). Another solution (its a bit "dirty") would be to
feed the signal to an output pin, delay it with an external RC network
and feed it in to the chip again.

/Peter

 

[cristian]

Hi,
I do agree with Pet and Mike, the best solution is 'snychronous delay'.
However, in case you still want to implement your code detailed above,
I think the only way that the synthesis tool keep the node is that the
node has to involve a logic operation.. For intance
buf2 <= buf1;
to keep buf2 as internal node, there has to be a logic operation on
the rigth hand side of the signal assignment:
buf2 <= buf1 xor signalb; -- the synthesis will keep buf2. (signalb
could a constant, but some constants are also optimized away... )

rgds,

cristian