S
Sudhir Singh
Guest
Hello, <BR>
I have been simulating a simple 1-bit register using Xilinx XST tools and ModelSim. The VHDL code implements a register with asynchronous reset (clear). The register gets mapped on to the Virtex-II IOB input FF. When I run the Post-Place and Route simulation, for some reason the FF output remains cleared for more than 100 ns before it starts to work properly. I am clocking the FF at 25 MHz. Changing the clock speed does not change this behaviour. The reset line is only asserted for one clock cycle during start up. <BR>
Also, changing the implementation to synchronous reset makes no difference. <BR>
Does anybody have any explanation for this behaviour?
I have been simulating a simple 1-bit register using Xilinx XST tools and ModelSim. The VHDL code implements a register with asynchronous reset (clear). The register gets mapped on to the Virtex-II IOB input FF. When I run the Post-Place and Route simulation, for some reason the FF output remains cleared for more than 100 ns before it starts to work properly. I am clocking the FF at 25 MHz. Changing the clock speed does not change this behaviour. The reset line is only asserted for one clock cycle during start up. <BR>
Also, changing the implementation to synchronous reset makes no difference. <BR>
Does anybody have any explanation for this behaviour?