Delay in Verilog for Asics design which is synthesizable

[mike12]

Can any help me for adding a simple delay of 10ns or more in verilog cod
which is synthesizable for asics design......
As #10ns etc are not synthesizable..



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[Rob Gaddi]

On Fri, 31 Aug 2012 11:30:36 -0500
"mike12" <3623@embeddedrelated> wrote:

Can any help me for adding a simple delay of 10ns or more in verilog code
which is synthesizable for asics design......
As #10ns etc are not synthesizable..



---------------------------------------
Posted through http://www.FPGARelated.com

Can you use a chain of flip-flops, or some other digitally quantized
thing? If not, then the answer is that you'll have to engage in analog
trickery; VCC servoed inverter chains or the like.

--
Rob Gaddi, Highland Technology -- www.highlandtechnology.com
Email address domain is currently out of order. See above to fix.

 

[Morten Leikvoll]

Can any help me for adding a simple delay of 10ns or more in verilog code
which is synthesizable for asics design......
As #10ns etc are not synthesizable..

First answer is just "NO". There is no way to do it, and there should be no
need for it on a proper synchronous design.
Using combinatorical delays is a really bad solution because it will be
dependant on fpga batch, environment (temperature, voltages), and internal
routing. You simply have very low guarantee that it will work on your next
design, or even tomorrow, when the wind has turned.

Second answer is "maybe".. if you have a DLL and a known clock available,
you may use the DLL's delay taps to generate it, but there should still be
no need for it.

Maybe you should explain why you need it? If its for i/o timing adjustments
of very few signals, I would recommend external passive delay lines, like
http://www.digikey.com/product-detail/en/DS1L5VJA00S-C/408-1122-ND/966403 .
As you see, they are not cheap. Also you need to be extra careful with
impedance matching on your pcb.

I have used with success a similar (but smd from Murata) 1.0ns delay on the
clock to get timing right for an external DVI transmitter chip.

 

[Hal Murray]

In article <na2dnSGNAKG8zdnNnZ2dnUVZ8hmdnZ2d@lyse.net>,

I have used with success a similar (but smd from Murata) 1.0ns delay on the
clock to get timing right for an external DVI transmitter chip.

1 ns is only 6 inches of routing.

--
These are my opinions. I hate spam.

 

[Morten Leikvoll]

I have used with success a similar (but smd from Murata) 1.0ns delay on
the
clock to get timing right for an external DVI transmitter chip.

1 ns is only 6 inches of routing.

True, but to be honest I didnt know the delay when pcb routing so I added
this general delay device and experimented.. (The chips datasheet does not
come with timing(!), only a reference to the SDVO (Intel) spec wich is not
public. Also, this carries up to 165Mhz clk, so I didn't want antenna
problems. At that specific design I didnt have a DLL available to tune it
either.

 

[Morten Leikvoll]

I have used with success a similar (but smd from Murata) 1.0ns delay on
the
clock to get timing right for an external DVI transmitter chip.

1 ns is only 6 inches of routing.

True, but to be honest I didnt know the delay when pcb routing so I added
this general delay device and experimented.. (The chips datasheet does not
come with timing(!), only a reference to the SDVO (Intel) spec wich is not
public. Also, this carries up to 165Mhz clk, so I didn't want antenna
problems. At that specific design I didnt have a DLL available to tune it
either.

Correction.. If any interest, it was the DVO spec, not SDVO.. And the chip
was the Sii 1178 in low swing mode.

 

[Jon]

First answer is just "NO". There is no way to do it, and there should be no

need for it on a proper synchronous design.

But if you really need to...

Instantiate a chain of buffers or delay cells. You wont be able to get a fixed delay of 10ns, but you maybe able to get at least 10ns (but it will most likely be more). The exact cell name will depend upon the cell library you are using. (For ARM libs, you'd want BUFXN or DLYXN).

For the instance names of the cells, add a pattern such as dont_touch to the instance name. E.g.

BUFX4 u_buf_1_dont_touch (.Y(t), .A(in));
BUFX4 u_buf_2_dont_touch (.Y(out), .A(t));

If you are using Design Compiler for synthesis, execute the following command after elaboration to prevent it from modifying them during synthesis:

set_dont_touch [get_cells -hier *dont_touch*]

If using RTL Compiler, you need to use set_attribute preserve.

Cheers,
Jon