DELAY in if statement

[dipesh.trivedi]

hi friends,
I want to include some delay under the if statement.
the code is like this
if (UARTGPIO_CODE_F4 == 1'b1)
begin
#200 TXD_d = 1'b1;
RXD_d = 1'b1;
RTS_d = 1'b0;
CTS_d = 1'b0;
#50 TXD_d = 1'b0;
RXD_d = 1'b0;
RTS_d = 1'b1;
CTS_d = 1'b1;
end
and i am getting error from compiler which are "Expecting the keyword
'end' [12.1.3(IEEE 2001)]."
can you suggest me how can i add delay in if statement...
waiting for your reply...

 

[Jonathan Bromley]

<dipesh.trivedi@gmail.com> wrote:

I want to include some delay under the if statement.
the code is like this
if (UARTGPIO_CODE_F4 == 1'b1)
begin
#200 TXD_d = 1'b1;
RXD_d = 1'b1;
RTS_d = 1'b0;
CTS_d = 1'b0;
#50 TXD_d = 1'b0;
RXD_d = 1'b0;
RTS_d = 1'b1;
CTS_d = 1'b1;
end
and i am getting error from compiler which are "Expecting the keyword
'end' [12.1.3(IEEE 2001)]."

That code fragment looks fine. I suspect you forgot to put it inside
an "initial" block, and therefore the compiler is treating it as a
generate. Your use of delays and if() is definitely correct.

Alternatively, perhaps that code appears inside another begin..end,
and you forgot the second closing "end" ?
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
jonathan.bromley@MYCOMPANY.com
http://www.MYCOMPANY.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.

 

[dipesh.trivedi]

hi Jonathan.
yes you are right. i was not using that if statement in always block
and thats why i was not able to compile it.
thanks you very much for the advice.
sorry i know it was a very silly question but as am very new to verilog
, so i have to understand other consequences of the language.

Jonathan Bromley wrote:

dipesh.trivedi@gmail.com> wrote:

I want to include some delay under the if statement.
the code is like this
if (UARTGPIO_CODE_F4 == 1'b1)
begin
#200 TXD_d = 1'b1;
RXD_d = 1'b1;
RTS_d = 1'b0;
CTS_d = 1'b0;
#50 TXD_d = 1'b0;
RXD_d = 1'b0;
RTS_d = 1'b1;
CTS_d = 1'b1;
end
and i am getting error from compiler which are "Expecting the keyword
'end' [12.1.3(IEEE 2001)]."

That code fragment looks fine. I suspect you forgot to put it inside
an "initial" block, and therefore the compiler is treating it as a
generate. Your use of delays and if() is definitely correct.

Alternatively, perhaps that code appears inside another begin..end,
and you forgot the second closing "end" ?
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
jonathan.bromley@MYCOMPANY.com
http://www.MYCOMPANY.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.