Delay element

[Henry]

Dear all,
I would like to implement a piplined logic. The code is like:
....
....
always @(posedge clk)
begin
tempa <= input;
tempb <= tempa;
tempc <= tempb;
output <= tempc;
end
....
....
However, the above code seems not efficient. The case would become
even worse if more pipeline stages are used. I would like to ask is it any
efficiency coding to implement the above pipelined logic?

Thank you very much!
Henry

 

[naren]

Hi Henry,
Try a 'generate-for' loop...
Rgds,
Naren.

TooMuch Semiconductor Solutions
#############################
Specialising in Verification Solutions

 

[gabor]

naren wrote:

Hi Henry,
Try a 'generate-for' loop...
Rgds,
Naren.

TooMuch Semiconductor Solutions
#############################
Specialising in Verification Solutions

You might also define a bit vector for your delay elements
and just do a shift like:

reg [8:1] delay_vector;

always @ (posedge clk)
begin
delay_vector <= {delay_vector[7:1],input};
end

Then delay_vector[n] would have n clock delays from the input.
Regards,
Gabor

 

[Henry]

thx all...

"gabor" <gabor@alacron.com>
???????:1152104928.367866.189180@b68g2000cwa.googlegroups.com...

naren wrote:
Hi Henry,
Try a 'generate-for' loop...
Rgds,
Naren.

TooMuch Semiconductor Solutions
#############################
Specialising in Verification Solutions

You might also define a bit vector for your delay elements
and just do a shift like:

reg [8:1] delay_vector;

always @ (posedge clk)
begin
delay_vector <= {delay_vector[7:1],input};
end

Then delay_vector[n] would have n clock delays from the input.
Regards,
Gabor