Delay assignment issue

  • Thread starter Kenneth Brun Nielsen
  • Start date
On Fri, 18 Sep 2009 04:10:43 -0700 (PDT), Kenneth Brun Nielsen wrote:

In short: making the assignment non-blocking did not change anything.
Click to expand...
In very short: I don't believe you.

In longer terms:
I have a for loop, that runs through a command file. When the read
command equals an input stimuli, the read values (which is a part of
the command) should be assigned to the inputs. The assignments should
happen while the test clock toggles (called cycleNo in previous post)
except for one assignment, which should be delayed 4 time units.
Click to expand...
So, try this simple test to see whether it does what you want:

reg [3:0] a, b;
reg clk;

// Make a stream of 5 clock pulses.
initial begin
clk = 0;
repeat (10) #5 clk = ~clk;
end

// Generate stimulus on a, b. It could
// come from a file, but let's use a count
// to keep the example simple.
initial begin
a = 0;
b = 0;
forever @(posedge clk) begin
$display("Detected a clock at time=%0d, $time);
a = a + 1; // should be synchronous with the clock
b <= #4 b - 1; // should be #4 later
$display("Done with the clock at time=%0d, $time);
end
end

always @(b)
$display ("b changed to %0d at time %0d", b, $time);

Try that and make sure it works the way you expect.

Now, here's the really important thing: If you change
"b <= #4 ...." to "b = #4 ..." you should find
that the second $display is postponed to 4 time units
after each clock. That's the difference between <=
and =. But if you change "b <= #4" to "b <= #14" then,
even though #14 is longer than a clock period, the
loop will execute on each clock edge as normal. It's the
updates on b that will be delayed.

Unfortunately I am not able to implement this delay. Neither with the
code posted earlier, OR with a non-blocking assignment (SCK <= #4
SCKi;). I think the problem is related to the combination of @
(cycleNo) and the delayed assignment.

I simulate in Icarus Verilog.
Click to expand...
Icarus generally gets the basic Verilog stuff right. It's
unlikely that is the problem.
--
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The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.
 
K

Kenneth Brun Nielsen

Guest
I'm trying to make a test bench environment, where input stimuli and a
set of other commands can be read from file.

So the file is read in a for loop and if it matches a stimili line,
then the values are assigned. In one case, I want to skew the signal.
This is my problem: I can not skew the signal SCK. Any suggestions for
a fix?

Here is a reduced test bench module:

module vd_test_tb;
// data input pins:
reg DI1, DI2, DI3, DI4,
DIN1, DIN2, DIN3, DIN4,
VT;
reg DI1i, DI2i, DI3i, DI4i,
DIN1i, DIN2i, DIN3i, DIN4i,
VTi;
// data output pins:
wire DO1, DO2, DO3, DO4;

wire DO1i, DO2i, DO3i, DO4i;
wire MISOi, INTi;


// control outputs:
wire INT, MISO;
// power domains:
wire GND, VDD;
// control inputs:
reg MOSI, SCK, SS;

// INTERNAL VALUES USED TO SKEW VALUES
reg SCKi;
reg SSi;
reg MOSIi;

integer fd,checkNum;
integer r,cycleNo;
reg initDone;
reg keepAliveMode, readMode;

reg [100*8-1:0] textline;
reg [50*8-1:0] subtext;

reg dummy;

assign GND = 1'b0;
assign VDD = 1'b1;

always #10 cycleNo = cycleNo+1;

initial
begin
fd = $fopen(`FILE ,"r");
cycleNo = 0;

while (!$feof(fd))
begin
if (!readMode)
begin
// THINGS CAN BE DONE HERE WITHOUT READING FURTHER LINES FROM THE
if (keepAliveMode)
begin
// ?
end
end
else
begin
r = $fgets(textline,fd);
if ($sscanf(textline, "%1b %1b %1b\n",SS,SCK,MOSI,DI1,DIN1) > 0
&& !initDone)
begin
// initialize input values
initDone = 1'b1;
$display("INPUT VALUES INITIALIZED");
end
else if ($sscanf(textline,"%1b %1b %1b
\n",SSi,SCKi,MOSIi,DI1i,DIN1i) > 0)
begin
// STIMULI READ.
// WAIT ONE TEST PERIOD BEFORE ASSIGNING
//$display("Stimuli read succesfully");
@(cycleNo);
SS = SSi;
MOSI = MOSIi;
SCK = #4 SCKi; // THIS IS MY PROBLEM
DI1 = DI1i;
DIN1 = DIN1i;
end
else if ($sscanf(textline,"* %s\n",subtext) > 0)
begin
$display("COMMENT READ: %s",subtext);
end
else if ($sscanf(textline,"%s\n",subtext) > 0)
begin
// THE COMMAND INPUT DOES NOT FIT ANY SUPPORTED FORMAT
$display("UNSUPPORTED INPUT FORMAT: %s", subtext);
end
else
$display("ERROR! INPUT LINE COULD NOT BE READ.");
end
end

THEDEVICE_TOP DUT1 (
.DO1(DO1i),
.INT(INT),
.MISO(MISO),
.GDS(GDS),
.GND(GND),
.VDD(VDD),
.VDS(VDS),
.DI1(DI1),
.DIN1(DIN1),
.MOSI(MOSI),
.SCK(SCK),
.SS(SS),
.VT(VT)
);
endmodule
 
On Sep 16, 3:23 pm, Kenneth Brun Nielsen
<kenneth.brun.niel...@googlemail.com> wrote:
I'm trying to make a test bench environment, where input stimuli and a
set of other commands can be read from file.

So the file is read in a for loop and if it matches a stimili line,
then the values are assigned. In one case, I want to skew the signal.
This is my problem: I can not skew the signal SCK. Any suggestions for
a fix?

Here is a reduced test bench module:

module vd_test_tb;
   // data input pins:
   reg DI1, DI2, DI3, DI4,
       DIN1, DIN2, DIN3, DIN4,
       VT;
   reg DI1i, DI2i, DI3i, DI4i,
       DIN1i, DIN2i, DIN3i, DIN4i,
       VTi;
   // data output pins:
   wire DO1, DO2, DO3, DO4;

   wire DO1i, DO2i, DO3i, DO4i;
   wire MISOi, INTi;

   // control outputs:
   wire INT, MISO;
   // power domains:
   wire GND, VDD;
   // control inputs:
   reg MOSI, SCK, SS;

   // INTERNAL VALUES USED TO SKEW VALUES
   reg SCKi;
   reg SSi;
   reg MOSIi;

   integer fd,checkNum;
   integer r,cycleNo;
   reg     initDone;
   reg     keepAliveMode, readMode;

   reg [100*8-1:0] textline;
   reg [50*8-1:0] subtext;

   reg            dummy;

   assign        GND = 1'b0;
   assign        VDD = 1'b1;

   always #10 cycleNo = cycleNo+1;

   initial
     begin
        fd = $fopen(`FILE ,"r");
        cycleNo = 0;

        while (!$feof(fd))
          begin
             if (!readMode)
               begin
                  // THINGS CAN BE DONE HERE WITHOUT READING FURTHER LINES FROM THE
                  if (keepAliveMode)
                    begin
                       // ?
                    end
               end
             else
               begin
                  r = $fgets(textline,fd);
                  if ($sscanf(textline, "%1b %1b %1b\n",SS,SCK,MOSI,DI1,DIN1) > 0
&& !initDone)
                    begin
                       // initialize input values
                       initDone = 1'b1;
                       $display("INPUT VALUES INITIALIZED");
                    end
                  else if ($sscanf(textline,"%1b %1b %1b
\n",SSi,SCKi,MOSIi,DI1i,DIN1i) > 0)
                    begin
                       // STIMULI READ.
                       // WAIT ONE TEST PERIOD BEFORE ASSIGNING
                       //$display("Stimuli read succesfully");
                       @(cycleNo);
                       SS = SSi;
                       MOSI = MOSIi;
                       SCK = #4 SCKi; // THIS IS MY PROBLEM
                       DI1 = DI1i;
                       DIN1 = DIN1i;
                    end
                  else if ($sscanf(textline,"* %s\n",subtext) > 0)
                    begin
                       $display("COMMENT READ: %s",subtext);
                    end
                  else if ($sscanf(textline,"%s\n",subtext) > 0)
                    begin
                       // THE COMMAND INPUT DOES NOT FIT ANY SUPPORTED FORMAT
                       $display("UNSUPPORTED INPUT FORMAT: %s", subtext);
                    end
                  else
                    $display("ERROR! INPUT LINE COULD NOT BE READ.");
               end
          end

   THEDEVICE_TOP DUT1 (
                     .DO1(DO1i),
                     .INT(INT),
                     .MISO(MISO),
                     .GDS(GDS),
                     .GND(GND),
                     .VDD(VDD),
                     .VDS(VDS),
                     .DI1(DI1),
                     .DIN1(DIN1),
                     .MOSI(MOSI),
                     .SCK(SCK),
                     .SS(SS),
                     .VT(VT)
                     );
   endmodule
Click to expand...
I think you should use non-blocking assignment.
 
On Sep 16, 9:32 am, Rakesh <rakeshbab...@gmail.com> wrote:
kenneth.brun.niel...@googlemail.com> wrote:
So the file is read in a for loop and if it matches a stimili line,
then the values are assigned. In one case, I want to skew the signal.
This is my problem: I can not skew the signal SCK. Any suggestions for
a fix?

                       SCK = #4 SCKi; // THIS IS MY PROBLEM

I think you should use non-blocking assignment.
Click to expand...
I agree; this is the most obvious solution. The syntax would be

SCK <= #4 SCKi; // Skew signal by #4

The distinction in behavior is given by the names of the constructs.
A blocking assignment blocks execution of the following statements
until the delay has occurred and the assignment has completed. A
nonblocking assignment does not block execution of the following
statement.
 
On 16 Sep., 15:32, Rakesh <rakeshbab...@gmail.com> wrote:

I think you should use non-blocking assignment.- Skjul tekst i anfřrselstegn -
Click to expand...
I tried that. Did not work as intended.
 
On Sep 16, 11:35 am, Kenneth Brun Nielsen
<kenneth.brun.niel...@googlemail.com> wrote:
On 16 Sep., 15:32, Rakesh <rakeshbab...@gmail.com> wrote:

I think you should use non-blocking assignment.

I tried that. Did not work as intended.
Click to expand...
Then you will have to be more specific about what you intended, or how
it worked differently from what you intended.
 
On 17 Sep., 18:06, sh...@cadence.com wrote:
On Sep 16, 11:35 am, Kenneth Brun Nielsen

kenneth.brun.niel...@googlemail.com> wrote:
On 16 Sep., 15:32, Rakesh <rakeshbab...@gmail.com> wrote:

I think you should use non-blocking assignment.

I tried that. Did not work as intended.

Then you will have to be more specific about what you intended, or how
it worked differently from what you intended.
Click to expand...
In short: making the assignment non-blocking did not change anything.

In longer terms:
I have a for loop, that runs through a command file. When the read
command equals an input stimuli, the read values (which is a part of
the command) should be assigned to the inputs. The assignments should
happen while the test clock toggles (called cycleNo in previous post)
except for one assignment, which should be delayed 4 time units.

Unfortunately I am not able to implement this delay. Neither with the
code posted earlier, OR with a non-blocking assignment (SCK <= #4
SCKi;). I think the problem is related to the combination of @
(cycleNo) and the delayed assignment.

I simulate in Icarus Verilog.

Best regards,
Kenneth
 
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