M
Manjunath Bhat
Guest
Hi,
I am trying to synthesize a verilog using Synopsys design compiler. I
use write_sdf command to write the delay annotated values to a file. I
would like to write minimum, typical and maximum delay values to the
SDF file so that I can use it in Verilog-XL for delay annotation.
However I find that most of the fime only min and max delay are
written; typical delay being same as minimum delay. Sometime the value
of minimum, typical and maximum delays are the same.
If you could suggest a way to overcome this, I would appreciate it
very much.
Thanks in advance,
Manjunath
I am trying to synthesize a verilog using Synopsys design compiler. I
use write_sdf command to write the delay annotated values to a file. I
would like to write minimum, typical and maximum delay values to the
SDF file so that I can use it in Verilog-XL for delay annotation.
However I find that most of the fime only min and max delay are
written; typical delay being same as minimum delay. Sometime the value
of minimum, typical and maximum delays are the same.
If you could suggest a way to overcome this, I would appreciate it
very much.
Thanks in advance,
Manjunath