delay and timing

[Amit]

Hello group,

Regarding (page 19) http://www.wolfsonmicro.com/uploads/documents/en/WM8731.pdf)

I have written a small code to generate those outputs (SCLK
and SDIN). However, since I'm new to Timing topic I will appreciate
it
if some of experts advise me on this.

The way I have understood it is that SCLK (or continuous square wave
in output) starts with t3 (where t3=600ns minimum) delay after SDIN.
However since the table represetns t3 as 600ns (MIN) so I conisidered
it as 1.3us instead. The reason I did this is because I have
considered SCLK low pulsewidth and high pulsewidth both as 1.3us.

Now, all I need to know:

Is it correct to generate the SCLK with a delay about 1.3us after
SDIN? or there are other issues that I'm missing?
if so, what are they and should I add them to the delay time?


Any suggestions or help will be appreciated greatly.

Amit

 

[Amit]

On Mar 31, 10:38 am, Amit <amit.ko...@gmail.com> wrote:

Hello group,

Regarding  (page 19)http://www.wolfsonmicro.com/uploads/documents/en/WM8731.pdf)

I have written a small code to generate those outputs (SCLK
and SDIN). However, since I'm new to Timing topic I will appreciate
it
if some of experts advise me on this.

The way I have understood it is that SCLK (or continuous square wave
in output) starts with t3 (where t3=600ns minimum) delay after SDIN.
However since the table represetns t3 as 600ns (MIN) so I conisidered
it as 1.3us instead. The reason I did this is because I have
considered SCLK low pulsewidth and high pulsewidth both as 1.3us.

Now, all I need to know:

Is it correct to generate the SCLK with a delay about 1.3us after
SDIN? or there are other issues that I'm missing?
if so, what are they and should I add them to the delay time?

Any suggestions or help will be appreciated greatly.

Amit

Thanks to Kenn I got my answer. Please ignore this thread.

Regards.