Guest
Hi all,
I am simulating a design with analog libs and verilog-a and verilog-
hdl under AMS configuration.
I have a delay (analoglib) that work fine when my simulation end of
time is less than 1ms, when I want to simulate longer time, the delay
block doesn't work...
I tried to setup the max delay to even 1e-15s (my delay is one quarter
of 14 gig) it still not work...
Do you know a know issue on this block ?
I am going to write a delay block in Verilog-a if I cannot solve
this...
THX
I am simulating a design with analog libs and verilog-a and verilog-
hdl under AMS configuration.
I have a delay (analoglib) that work fine when my simulation end of
time is less than 1ms, when I want to simulate longer time, the delay
block doesn't work...
I tried to setup the max delay to even 1e-15s (my delay is one quarter
of 14 gig) it still not work...
Do you know a know issue on this block ?
I am going to write a delay block in Verilog-a if I cannot solve
this...
THX