Definition of nets and subnets

[vlsidesign]

Maybe this is the wrong forum for the question, but I am trying to
understand Cadence connectivity model better, and I think some of my
confusion is because I should better understand netlisting.

When do you mainly get subnets? Is it when you have a bus? If so, what
is the net called and what are the subnets?

For example,
Is there one net called 'bus[3:0]' that has four subnets called
bus[0], bus[1], bus[2] and bus[3]?

 

[vlsidesign]

On May 16, 5:49 pm, vlsidesign <ford...@gmail.com> wrote:

Maybe this is the wrong forum for the question, but I am trying to
understand Cadence connectivity model better, and I think some of my
confusion is because I should better understand netlisting.

When do you mainly get subnets? Is it when you have a bus? If so, what
is the net called and what are the subnets?

For example,
Is there one net called 'bus[3:0]' that has four subnets called
bus[0], bus[1], bus[2] and bus[3]?

I think I found the information that has answered my question. The
bus[3:0] would seem to be four "terminals", which would then be four
separate nets. I included some information and there reference, in
case it may be useful for others.

-------------- vlehelp.pdf, page 222-223
Terminals expose a net up to the next level of the hierarchy. For
example, a master might have
10 nets and 4 terminals (associated with 4 of the nets).

When you create an instance of a master, it may have objects called
instTerms associated
with it. These instTerms map terminals in the instance’s master to
nets of the cellview in which
the instance has been placed. Virtuoso XL (or the Pick and Place
command) creates and
assigns these instTerms automatically. To expose these nets to the
next level of the hierarchy,
you create terminals for the nets, which are then mapped using
instTerms at the next level.

For example, consider the instance in the following figure, which
contains five pins: two on net
A, two on net B, and one on net C. These nets need to be available at
the next level of the
hierarchy, so you create three terminals named A, B, and C. 1


-------------- VXLConnAn.pdf, page 6-7
The term terminal corresponds to a logical connection in the symbolic
view of a device. The
term pin refers to a physical shape assigned to that terminal in the
layout.

As stated above, a single terminal on a device can have a number of
physical
pins.

 

[Riad KACED]

Hi There,

The notation 'bus[3:0]' is not supported by spectre I'm afraid. You
can write 'bus<3:0>' rather.
This will be netlisted as: bus_0, bus_1, bus_2 and bus_3

Cheers,
Riad.

 

[S. Badel]

I think I found the information that has answered my question. The
bus[3:0] would seem to be four "terminals", which would then be four
separate nets. I included some information and there reference, in
case it may be useful for others.

That sounds incorrect.

As the doc explains, terminals are logical connection points between a cell and the upper level of
hierarchy, i.e. it is where the signals come in and out of a cell.

Any net can be associated with a terminal, or not, regardless of its nature. So having a bus does
not necessarily imply terminals. Neither subnets, for that matter.

The exact, complete definition of a subnet is not that clear to me, I must say. What I can say is,
any net can have a number of subnets (which are nets themselves), and all are electrically
connected. Subnets represents distinct parts of a net which have different properties, they are used
for example in the modeling of strong/weak electrical connections between different parts of a net.

Regarding your example of the bus, when you create a bus 'bus<3:0>' you get a single net 'bus<3:0>',
and four *signals* 'bus<3>' ... 'bus<0>'.


Cheers,
Stéphane

 

[Andrew Beckett]

S. Badel wrote, on 05/19/08 10:17:

I think I found the information that has answered my question. The
bus[3:0] would seem to be four "terminals", which would then be four
separate nets. I included some information and there reference, in
case it may be useful for others.

That sounds incorrect.

As the doc explains, terminals are logical connection points between a
cell and the upper level of hierarchy, i.e. it is where the signals come
in and out of a cell.

Any net can be associated with a terminal, or not, regardless of its
nature. So having a bus does not necessarily imply terminals. Neither
subnets, for that matter.

The exact, complete definition of a subnet is not that clear to me, I
must say. What I can say is, any net can have a number of subnets (which
are nets themselves), and all are electrically connected. Subnets
represents distinct parts of a net which have different properties, they
are used for example in the modeling of strong/weak electrical
connections between different parts of a net.

Regarding your example of the bus, when you create a bus 'bus<3:0>' you
get a single net 'bus<3:0>', and four *signals* 'bus<3>' ... 'bus<0>'.


Cheers,
Stéphane

Be careful. subnets are essentially there as a means of handling the rather
convoluted pin connection model in CDB - i.e. weak connects, must-connects,
strong-connects. In OA there is a _much_ more logical model of pin connectivity
model which doesn't involve subnets, so be warned - this stuff is changing.

In general you manipulate the subnets by using the functions for
creating strong groups and so on.

As a result of this difference, OA allows multiple figures per pin (that's how
strongly connected pins are handled), as well as multiple terminals per net
(allows "through" connections in the database). Strong connections in OA end
up as separate nets and terminals - but there is some additional data to tie
them together. I'm not going to fully discuss this here - it's in the
documentation.

Nets and signals are different though - a net may or may not be a vector,
whereas a signal is always scalar. So for each bus net, you'll get each of the
bits as a scalar signal too. That's true in OA as well.

Just wanted to point this out to avoid anyone delving too hard and building
in stuff that is locked to CDB...

Regards,

Andrew.