defining a flag-dependent constant

[valentin tihomirov]

I desided to define an integer constant in the package.

package PKG is
constant FLAG: Boolean := True;
constant WIDTH := FLAG ? N1 : UTILS.BITS_TO_FIT(N2);
end package;

architecture A of E is
signal S: std_logic_vector(PKG.WIDTH-1 downto 0);


The only bypass I see is to replace the constant with GET_WIDTH function.

 

[Mike Treseler]

valentin tihomirov wrote:

I desided to define an integer constant in the package.

package PKG is
constant FLAG: Boolean := True;
constant WIDTH := FLAG ? N1 : UTILS.BITS_TO_FIT(N2);
end package;

architecture A of E is
signal S: std_logic_vector(PKG.WIDTH-1 downto 0);


The only bypass I see is to replace the constant with GET_WIDTH function.

A function returning a constant
would work using IF, THEN, END IF;
There is no "a ? b : c" in vhdl.

WIDTH could also be a generic constant of E.

-- Mike Treseler

 

[Marcus Harnisch]

Hi Valentin,

You could wait for ternary operators in VHDL-200X or you could try
this instead:

package p is

function if_else (cond : boolean;
result_if : positive;
result_else : positive)
return positive;

constant FLAG : boolean;
constant width : positive;

end package p;

package body p is

function if_else (cond : boolean;
result_if : positive;
result_else : positive)
return positive is
begin
if (cond) then
return result_if;
else
return result_else;
end if;
end function if_else;

constant FLAG : boolean := true;
constant width : positive := if_else(FLAG, 16, 32);

end package body p;


Best regards,
Marcus

 

[Jim Lewis]

Valentin,
I would use the function suggested by Marcus and then
when VHDL-200X is standardized submit the code snippet
to your eda vendor as a evidence for your need for
the new features of VHDL-200X.

What we are finding is that vendors don't implement a
new feature just because it is in a standard. They
implement it when they get requests from customers who
have a compelling need for the feature.

Best Regards,
Jim Lewis
VHDL-200X Fast Track co-team leader
--
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Jim Lewis
Director of Training mailto:Jim@SynthWorks.com
SynthWorks Design Inc. http://www.SynthWorks.com
1-503-590-4787

Expert VHDL Training for Hardware Design and Verification
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

Hi Valentin,

You could wait for ternary operators in VHDL-200X or you could try
this instead:

package p is

function if_else (cond : boolean;
result_if : positive;
result_else : positive)
return positive;

constant FLAG : boolean;
constant width : positive;

end package p;

package body p is

function if_else (cond : boolean;
result_if : positive;
result_else : positive)
return positive is
begin
if (cond) then
return result_if;
else
return result_else;
end if;
end function if_else;

constant FLAG : boolean := true;
constant width : positive := if_else(FLAG, 16, 32);

end package body p;


Best regards,
Marcus