`define Multipl Instantiatons

[terabits]

Hi

This may be a very fundamental question.
Well my requirement is i have a module which should be instantiated
multiple times depending upon the `define.
let us say module is m m1 (a,b,c);

`define m4
so i need to instantiate this module 4times

`ifdef m4
`define m3
`define m2
`define m1
m m1(a,b,c);
`ifdef m3
`define m2
`define m1
m m2(a1,b1,c1);
`ifdef m2
`define m1
m m3 (a2,b2,c2);
`ifdef m1
m m4 (a3,b3,c3);
`endif
`endif
`endif
`endif

this looks simple for 4 or 3, if i have to do it for 20 times my code
looks so ugly........
if define is 3 i want to do it 3 times if 2 to 2 times and so on.
hence i did this way this look awkward to me there must be simple
solution for this, any one help me !!!!!

rgds

 

[terabits]

A small correction

Hi

This may be a very fundamental question.
Well my requirement is i have a module which should be instantiated
multiple times depending upon the `define.
let us say module is m m1 (a,b,c);

`define m4
so i need to instantiate this module 4times

`ifdef m4
`define m3

m m1(a,b,c);
`ifdef m3
`define m2

m m2(a1,b1,c1);
`ifdef m2
`define m1
m m3 (a2,b2,c2);
`ifdef m1
m m4 (a3,b3,c3);
`endif
`endif
`endif
`endif

this looks simple for 4 or 3, if i have to do it for 20 times my code
looks so ugly........
if define is 3 i want to do it 3 times if 2 to 2 times and so on.
hence i did this way this look awkward to me there must be simple
solution for this, any one help me !!!!!

rgds

 

[Jonathan Bromley]

On 15 Mar 2007 10:24:21 -0700, "terabits" <tera.bits@gmail.com> wrote:

Hi

This may be a very fundamental question.
Well my requirement is i have a module which should be instantiated
multiple times depending upon the `define.
let us say module is m m1 (a,b,c);

Can you use a generate? Or an instance array?
In either situation it would probably be necessary to create an
array (or vector) of signals for each connection.

If you need completely different signal names to connect to
each instance, then it is VERY troublesome, as you say.
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
jonathan.bromley@MYCOMPANY.com
http://www.MYCOMPANY.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.

 

[terabits]

Can you use a generate? Or an instance array?
In either situation it would probably be necessary to create an
array (or vector) of signals for each connection.

If you need completely different signal names to connect to
each instance, then it is VERY troublesome, as you say.
--
yeah i need different set of signals for each instantiation, !!!!

instance array ? what do u mean by that ?

 

[Zanan]

Not that this helps your real question, but Verilog-2001's preprocessor adds
`elsif

`ifdef X
blahblah
`elsif Y
blahblah2
`elsif Z
blahblah3
`endif // nice and clean, only 1 endif!

instance array ? what do u mean by that ?

module my_xor(x,y,z);
input x;
input y;
output z;
assign z = y ^ x;
endmodule

module my_xor4(x,y,z)
input [3:0] xvec;
input [3:0] yvec;
output [3:0] zvec;

my_xor xors[3:0] (.x(xvec), .y(yvec), .z(zvec) );

/* alternative, if you have Verilog-2001 simulator...
genvar g;
generate for( g = 0; g < 4; g = g + 1 ) begin : h // <- yes, you need this
dummy label! (I used 'h')
my_xor xors( .x(xvec[g]), .y(yvec[g]), .z(zvec[g]) );
end
endgenerate
*/

endmodule

 

On Mar 15, 9:22 pm, "Zanan" <Z...@nowhere.net> wrote:

Not that this helps your real question, but Verilog-2001's preprocessor adds
`elsif

`ifdef X
blahblah
`elsif Y
blahblah2
`elsif Z
blahblah3
`endif // nice and clean, only 1 endif!



instance array ? what do u mean by that ?

module my_xor(x,y,z);
input x;
input y;
output z;
assign z = y ^ x;
endmodule

module my_xor4(x,y,z)
input [3:0] xvec;
input [3:0] yvec;
output [3:0] zvec;

my_xor xors[3:0] (.x(xvec), .y(yvec), .z(zvec) );

/* alternative, if you have Verilog-2001 simulator...
genvar g;
generate for( g = 0; g < 4; g = g + 1 ) begin : h // <- yes, you need this
dummy label! (I used 'h')
my_xor xors( .x(xvec[g]), .y(yvec[g]), .z(zvec[g]) );
end
endgenerate
*/

thaz cool can i do this, i wonder how i keep track of each
instantiation.
like my_xor module has a task. i want to use it with different
instantiations.
xor1.task
xor2,task can i do this ???

and when u say my_xor xors (.x.....) will the instantiation name
same ???

rgds