M
Moises
Guest
Hi everybody!
My name is Moises and now I am synthesizing a design in VHDL. My
problem is that I am using Sinplicity for that purpose but I do not
know how to define the output of a combinatorial net as a clock. This
net is not in the top level file, but in a third one, that is:
top level file: ahb_block.vhd
second level file: spacewire.vhd (instantiated in ahb_block.vhd)
third levl file: sp.vhd (instantiated in spacewire.vhd) ---> this is
here where the combinatorial logic is!!
I have tried the following sentences, but it does not work at all:
define_clock n:ahb_block.spacewire.sp.clock_rx -freq 66
define_clock n:ahb_block|spacewire|sp.clock_rx -freq 66
Does anybody know how to solve this problem?
Thank you very much for your help.
Moises
My name is Moises and now I am synthesizing a design in VHDL. My
problem is that I am using Sinplicity for that purpose but I do not
know how to define the output of a combinatorial net as a clock. This
net is not in the top level file, but in a third one, that is:
top level file: ahb_block.vhd
second level file: spacewire.vhd (instantiated in ahb_block.vhd)
third levl file: sp.vhd (instantiated in spacewire.vhd) ---> this is
here where the combinatorial logic is!!
I have tried the following sentences, but it does not work at all:
define_clock n:ahb_block.spacewire.sp.clock_rx -freq 66
define_clock n:ahb_block|spacewire|sp.clock_rx -freq 66
Does anybody know how to solve this problem?
Thank you very much for your help.
Moises