Default values for Verilog task arguments

[Andrew Mazin]

Hi All,

I would like to use default values for unspecified verilog task arguments.
For example, I've created the task:

task my_task;
input a;
input b;
input c;

integer a, b;

......
endtask

While running this task, I am passing 2 (not 3!) arguments to it, such as:

my_task(1,2);
Verilog accepts this, assigning value "x" to c.

Then, I am trying to write something like:

task my_task;
input a;
input b;
input c;

integer a, b;
begin
if (c == 1'bx) c = 1;
......
endtask

in order to set default value for c, but this doesn't work.

Is there a way to set default value for unspecified verilog task argument?

Thanks,
-Andrew

 

[Arjuna Wijesurendra]

Andrew Mazin wrote:

Hi All,

I would like to use default values for unspecified verilog task arguments.
For example, I've created the task:

task my_task;
input a;
input b;
input c;

integer a, b;

.....
endtask

While running this task, I am passing 2 (not 3!) arguments to it, such as:

my_task(1,2);
Verilog accepts this, assigning value "x" to c.

Then, I am trying to write something like:

task my_task;
input a;
input b;
input c;

integer a, b;
begin
if (c == 1'bx) c = 1;
.....
endtask

in order to set default value for c, but this doesn't work.

You need to use the case equality operator === in order to compare against any
'x's or 'z's.

Hope this helps,
Arjuna

 

[Steven Sharp]

andrew119@canada.com (Andrew Mazin) wrote in message news:<725b2b95.0309081322.c569bad@posting.google.com>...

I would like to use default values for unspecified verilog task arguments.

While running this task, I am passing 2 (not 3!) arguments to it, such as:

my_task(1,2);
Verilog accepts this, assigning value "x" to c.

The Verilog language does not support unspecified task arguments. Leaving
out arguments is illegal Verilog code. If your simulator is not producing
an error for this, then it is incorrect.

It is quite likely that your simulator is not assigning a value of x
to c. It probably isn't assigning anything at all. The value of c
starts out x at the beginning of simulation. If your first call
doesn't assign anything to it, then it will still be x. However, if
you assign a value to c (directly or with a call), and then don't
pass anything on the next call, it is probably just keeping the same
value it had at the end of the previous call.

 

[Andrew Mazin]

Jim,
Arjuna,
thanks!

However, now I have another problem.
I am usng corrected task:

task my_task;
input a;
input b;
input c;

integer a, b;
begin
if (c === 1'bx) c = 0;
$display("c = %b", c);
.....
endtask

and I am calling it multiple times, such as:

initial begin
my_task(1,2,1);
my_task(3,4);
my_task(5,6);
....
end

If "c" was defined in the first task, it propagates defined value to
consequent task calls, overriding default value. So, my log file will
be:
c = 1
c = 1
c = 1
instead of expected:
c = 1
c = 0
c = 0

I am using NC Verilog.

Thanks,
-Andrew

 

[Steven Sharp]

andrew119@canada.com (Andrew Mazin) wrote in message news:<725b2b95.0309090758.4da20dcd@posting.google.com>...

I am using NC Verilog.

When I tested your example code in NC-Verilog, it produced an error:

mytask(3,4);
|
ncvlog: *E,TOOFAC (xxx.v,16|11): too few actual arguments [10.2.2][10.3(IEEE)].

I tried this in versions from 3.3 to 5.0, and all correctly caught this
error in your code.

Either you are using a different version that contains a bug in this area
(highly unlikely, since this check has not been changed) or your testcase
is different in some way from the example code you have posted. I would
suggest filing a bug report, including the exact version of the simulator
and the testcase where it failed to catch the missing arguments.

To reiterate: Verilog requires providing values for all arguments to a
Verilog task. Your example is invalid Verilog code.

 

[Andrew Mazin]

Stephen,

Thank you for reply.
Here is simple example illustrating this bug:

module test;
my_module my_module ();
initial begin
my_module.my_task(1,2,3);
my_module.my_task(2,3);
my_module.my_task(3);
$finish;
end
endmodule

module my_module ();
task my_task;
input a;
input b;
input c;
integer a,b,c;
begin
$display("a = %0d, b = %0d, c = %0d", a, b, c);
end
endtask
endmodule

There is NO compilation errors and simulation produces the following
results:

a = 1, b = 2, c = 3
a = 2, b = 3, c = 3
a = 3, b = 3, c = 3
Simulation complete via $finish(1) at time 0 FS + 0

As you may see, I can pass 1 or 2 arguments to the task and it is
still OK. Only in a case I give more than 3 or no arguments, I get
compilation error.
I am using NCVerilog 4.1

Thanks,
-Andrew

 

[Steven Sharp]

andrew119@canada.com (Andrew Mazin) wrote in message news:<725b2b95.0309101329.5b25a4ef@posting.google.com>...

Here is the difference:

my_module.my_task(2,3);

The original example code that you posted was calling a task declared
in the same module as the call. The missing arguments were caught during
compilation and produced an error.

In your actual testcase, you are calling a task declared in a different
module instance, using a hierarchical name. This cannot be checked
during initial compilation of the source code. It must wait until the
design is elaborated, when the non-local task instance associated with
the particular hierarchical name is resolved. Apparently this later
check is not complete enough.

I have filed a bug report against this failure to catch missing
arguments in an out-of-module call. You may wish to report this
through normal channels as well.