Default input value

[mjl296@hotmail.com]

In synthesisable code, is it possible to give a default value to a
module input, such that if it is not connected it will get the default
value rather than Z?

Thanks,

Mark

 

[Jonathan Bromley]

On Fri, 21 Sep 2007 13:17:18 -0000, "mjl296@hotmail.com"
<mjl296@hotmail.com> wrote:

In synthesisable code, is it possible to give a default value to a
module input, such that if it is not connected it will get the default
value rather than Z?

Not as far as I'm aware.

You can easily do so by putting a pullup or pulldown
on the port net inside the module, BUT that is not
synthesisable by any tool I know about.

S'pose you could use VHDL instead
--
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[Kevin Neilson]

Jonathan Bromley wrote:

On Fri, 21 Sep 2007 13:17:18 -0000, "mjl296@hotmail.com"
mjl296@hotmail.com> wrote:

In synthesisable code, is it possible to give a default value to a
module input, such that if it is not connected it will get the default
value rather than Z?

Not as far as I'm aware.

You can easily do so by putting a pullup or pulldown
on the port net inside the module, BUT that is not
synthesisable by any tool I know about.

S'pose you could use VHDL instead

In a Xilinx part, you can specify a pullup or pulldown on an input pin
so it will pull to a default when not driven. But you can only do this
if the hardware supports it.