default case synthesis (Espresso BLIF)

Hi,
Does the blif format, or more specifically Espresso PLA format
accept "default" case.

For example in verilog, how would I go about specifying

begin
case ( sel_inp )
3'h7 : E_724 = 1'h1 ;
3'h6 : E_724 = 1'h1 ;
3'h5 : E_724 = 1'h1 ;
3'h4 : E_724 = 1'h1 ;

default : E_724 = 1'h0 ;
endcase

Is it possible to specify default case to PLA, or do I have to
enumerate over all the values?

Please helpp... I'm stuck in this