decoupling caps placement

[tempus fugit]

Hey all;

I've got a circuit that uses 3 4049 inverters. On this IC, the V+ is on pin
8 and the ground is on pin 1. I know that the decoupling caps need to be as
close to the IC as possible, but how can I connect 1 end of the cap to V+
and the other to ground when the pins are so far away? Is it sufficient to
connect 1 end of the cap to V+ and the other to a nearby ground node, or
should the cap be connected close to the actual ground pin of the IC? Also,
do I use 1 cap for each IC? If so, (the ICs are fairly close together)
wouldn't the IC "see" the caps as being the paralleled value of the 3 caps,
thus reducing the available capacitance? I was going to use 0.1uF for the
value of each decoupling cap. Would it also be wise to use a larger (1uF or
higher) cap in parallel?

Thanks

 

[ian field]

"tempus fugit" <toccata@quitspammingme.ciaccess.com> wrote in message
news:1b084$494eb60b$d1d89b66$25834@PRIMUS.CA...

Hey all;

I've got a circuit that uses 3 4049 inverters. On this IC, the V+ is on
pin
8 and the ground is on pin 1. I know that the decoupling caps need to be
as
close to the IC as possible, but how can I connect 1 end of the cap to V+
and the other to ground when the pins are so far away? Is it sufficient to
connect 1 end of the cap to V+ and the other to a nearby ground node, or
should the cap be connected close to the actual ground pin of the IC?
Also,
do I use 1 cap for each IC? If so, (the ICs are fairly close together)
wouldn't the IC "see" the caps as being the paralleled value of the 3
caps,
thus reducing the available capacitance? I was going to use 0.1uF for the
value of each decoupling cap. Would it also be wise to use a larger (1uF
or
higher) cap in parallel?

Thanks

Sometimes I've seen capacitor strips that can be cut to length, but never
did find a supplier.

Some types of IC socket have an open centre that you can mount a small
capacitor diagonally, normally 0.1uF non-electrolytics (very low ESR) are ok
if you decouple every chip as long as you fit a few electrolytics
distributed around the board.

 

[BobW]

"tempus fugit" <toccata@quitspammingme.ciaccess.com> wrote in message
news:1b084$494eb60b$d1d89b66$25834@PRIMUS.CA...

Hey all;

I've got a circuit that uses 3 4049 inverters. On this IC, the V+ is on
pin
8 and the ground is on pin 1. I know that the decoupling caps need to be
as
close to the IC as possible, but how can I connect 1 end of the cap to V+
and the other to ground when the pins are so far away? Is it sufficient to
connect 1 end of the cap to V+ and the other to a nearby ground node, or
should the cap be connected close to the actual ground pin of the IC?
Also,
do I use 1 cap for each IC? If so, (the ICs are fairly close together)
wouldn't the IC "see" the caps as being the paralleled value of the 3
caps,
thus reducing the available capacitance? I was going to use 0.1uF for the
value of each decoupling cap. Would it also be wise to use a larger (1uF
or
higher) cap in parallel?

Thanks

The purpose of the decoupling capacitors is to insure that ICs maintain
sufficient supply voltage during those times when time-varying currents flow
through the supply pins. This time-varying current is mathematically
referred to as di/dt (the rate of change of current with respect to time).

The voltage lost during these time-varying events is:

V=L*di/dt

where L is the inductance around the loop where this current flows.

The longer the path is from a capacitor to the IC then the larger L is.

However, in your case, these 4049s, due to their intrinsically-low di/dt and
the di/dt caused by their loads, should have a fairly small total di/dt for
each IC/cap combination.

So, don't worry too much about the copper paths between the IC's VCC, GND,
and the capacitors. Just keep the copper fairly thick. You can utilize any
local VCC and/or GND plane, too.

You have to know a lot about your di/dt requirements, the characteristics of
a given capacitor, and the IC supply tolerance in order to make an accurate
assessment of what type and size of capacitor to use. For your design, a
0.1uF ceramic cap per IC will work fine.

Most designers start out their designs with each IC having its own bypass
cap(s). Only after the layout process begins will we make judgments as to
whether or not the total number of caps can be reduced.

Bob

--
== All google group posts are automatically deleted due to spam ==

 

[Jamie]

tempus fugit wrote:

Hey all;

I've got a circuit that uses 3 4049 inverters. On this IC, the V+ is on pin
8 and the ground is on pin 1. I know that the decoupling caps need to be as
close to the IC as possible, but how can I connect 1 end of the cap to V+
and the other to ground when the pins are so far away? Is it sufficient to
connect 1 end of the cap to V+ and the other to a nearby ground node, or
should the cap be connected close to the actual ground pin of the IC? Also,
do I use 1 cap for each IC? If so, (the ICs are fairly close together)
wouldn't the IC "see" the caps as being the paralleled value of the 3 caps,
thus reducing the available capacitance? I was going to use 0.1uF for the
value of each decoupling cap. Would it also be wise to use a larger (1uF or
higher) cap in parallel?

Thanks



In our day we call them by pass cap's and as far as i'm concerned,

they still are.

As on your question. I've found that the by pass cap really helps
in removing load variations from a previous path from another component
that may also be taxing the rail and causing unstable voltages. Placing
by pass caps between the components as you go along normally cures it.
Unless you're trying to work with high freq R.F. design, I don't
think having a little lead way isn't going to hurt any.

1 uf or more for load swing variations and ~ .01 non inductive type
for R.F. issues.
Many times, you'll see a combination of 2 types in a single location.

http://webpages.charter.net/jamie_5"

 

[Andrew Holme]

"tempus fugit" <toccata@quitspammingme.ciaccess.com> wrote in message
news:1b084$494eb60b$d1d89b66$25834@PRIMUS.CA...

do I use 1 cap for each IC? If so, (the ICs are fairly close together)
wouldn't the IC "see" the caps as being the paralleled value of the 3
caps,
thus reducing the available capacitance?

They're not like resistors. Parallel capacitance adds:

C1 || C2 || C3 = C1 + C2 + C3

 

[www.interfacebus.com]

On Dec 21, 4:33 pm, "tempus fugit"
<tocc...@quitspammingme.ciaccess.com> wrote:

Hey all;

I've got a circuit that uses 3 4049 inverters. On this IC, the V+ is on pin
8 and the ground is on pin 1. I know that the decoupling caps need to be as
close to the IC as possible, but how can I connect 1 end of the cap to V+
and the other to ground when the pins are so far away? Is it sufficient to
connect 1 end of the cap to V+ and the other to a nearby ground node, or
should the cap be connected close to the actual ground pin of the IC? Also,
do I use 1 cap for each IC? If so, (the ICs are fairly close together)
wouldn't the IC "see" the caps as being the paralleled value of the 3 caps,
thus reducing the available capacitance? I was going to use 0.1uF for the
value of each decoupling cap. Would it also be wise to use a larger (1uF or
higher) cap in parallel?

Thanks

Place the cap near the voltage pin of the IC, so the lead/trace
between the Vcc pin and capacitor is as short as possible. Ground the
other end of the cap to the nearest ground point.

As the capacitor supplies voltage to the IC either for switching or
ripple reduction the voltage is supplied at the pin of the IC, and not
inches aways.

It dosen't hurt to add two caps in parallel;
http://www.interfacebus.com/Compound_Capacitor_By-Passing.html

 

[Tim Wescott]

On Sun, 21 Dec 2008 16:33:47 -0500, tempus fugit wrote:

Hey all;

I've got a circuit that uses 3 4049 inverters. On this IC, the V+ is on
pin 8 and the ground is on pin 1. I know that the decoupling caps need
to be as close to the IC as possible, but how can I connect 1 end of the
cap to V+ and the other to ground when the pins are so far away? Is it
sufficient to connect 1 end of the cap to V+ and the other to a nearby
ground node, or should the cap be connected close to the actual ground
pin of the IC? Also, do I use 1 cap for each IC? If so, (the ICs are
fairly close together) wouldn't the IC "see" the caps as being the
paralleled value of the 3 caps, thus reducing the available capacitance?
I was going to use 0.1uF for the value of each decoupling cap. Would it
also be wise to use a larger (1uF or higher) cap in parallel?

Thanks

For that chip a 100nF (0.1u) ceramic up by pin 1, with a lead straight to
pin 1 and another one straight to pin 8 will be more than sufficient.

You can think about reducing them later -- but why? Unless you're trying
to shave deci-pennies off of the board cost, it's better to have too many
bypass caps than just enough.

--
Tim Wescott
Control systems and communications consulting
http://www.wescottdesign.com

Need to learn how to apply control theory in your embedded system?
"Applied Control Theory for Embedded Systems" by Tim Wescott
Elsevier/Newnes, http://www.wescottdesign.com/actfes/actfes.html

 

[Michael A. Terrell]

tempus fugit wrote:

Hey all;

I've got a circuit that uses 3 4049 inverters. On this IC, the V+ is on pin
8 and the ground is on pin 1. I know that the decoupling caps need to be as
close to the IC as possible, but how can I connect 1 end of the cap to V+
and the other to ground when the pins are so far away? Is it sufficient to
connect 1 end of the cap to V+ and the other to a nearby ground node, or
should the cap be connected close to the actual ground pin of the IC? Also,
do I use 1 cap for each IC? If so, (the ICs are fairly close together)
wouldn't the IC "see" the caps as being the paralleled value of the 3 caps,
thus reducing the available capacitance? I was going to use 0.1uF for the
value of each decoupling cap. Would it also be wise to use a larger (1uF or
higher) cap in parallel?

Thanks

<http://parts.digikey.com/1/parts/297556-econo-socket-w-cap-tin-st-16-pin-ed16dt-ca.html>

<http://media.digikey.com/pdf/Data%20Sheets/On%20Shore%20PDFs/ED-yyDT-CA.pdf>


--
http://improve-usenet.org/index.html

aioe.org, Goggle Groups, and Web TV users must request to be white
listed, or I will not see your messages.

If you have broadband, your ISP may have a NNTP news server included in
your account: http://www.usenettools.net/ISP.htm


There are two kinds of people on this earth:
The crazy, and the insane.
The first sign of insanity is denying that you're crazy.

 

[David L. Jones]

On Dec 22, 8:33 am, "tempus fugit"
<tocc...@quitspammingme.ciaccess.com> wrote:

Hey all;

I've got a circuit that uses 3 4049 inverters. On this IC, the V+ is on pin
8 and the ground is on pin 1. I know that the decoupling caps need to be as
close to the IC as possible, but how can I connect 1 end of the cap to V+
and the other to ground when the pins are so far away?

There are many ways to do this depending on how your board and circuit
are layed out.

For instance, on say 2 layer boards it's common to have a "power
strip" going underneath the IC that feeds ground and power to a whole
row of chips end-on-end, so you can put the cap at the end of the chip
in this case.

When you go to multiple layer board you usually have a ground plane
that provides a nice low impedance ground path for you. So in this
case you would put the cap next to the positive power pin and then to
the ground plane.

Other circuit topologies may dictate something different again.

Is it sufficient to
connect 1 end of the cap to V+ and the other to a nearby ground node, or
should the cap be connected close to the actual ground pin of the IC?

Ideally it should be the ground pin of the IC. But in your case any
nearby ground node will almost certainly do. A 4049 is not a fast
device, so it's not likely to be at all critical.

What you are after is (simplistically) the shortest electrical "loop"
path between the positive power pin, through your decoupling cap, and
back to the ground pin on the chip. The shorter the better.

Also, do I use 1 cap for each IC?

That's the general rule of thumb, yes.

If so, (the ICs are fairly close together)
wouldn't the IC "see" the caps as being the paralleled value of the 3 caps,
thus reducing the available capacitance?

It's not just the capacitance, it's the inductance (and resistance) of
the entire power/ground "loop" that matters. It's a complex thing.

I was going to use 0.1uF for the
value of each decoupling cap. Would it also be wise to use a larger (1uF or
higher) cap in parallel?

This is complex area and has to do with all sorts of factors.
Generally, if the datasheet for your device does not specifically say
so, then one cap will be sufficient. If it's critical, then the
datasheet might recommend two or three caps of different values and
types.

Dave.

 

[Eeyore]

tempus fugit wrote:

Hey all;

I've got a circuit that uses 3 4049 inverters. On this IC, the V+ is on pin
8 and the ground is on pin 1. I know that the decoupling caps need to be as
close to the IC as possible, but how can I connect 1 end of the cap to V+
and the other to ground when the pins are so far away?

With a 4049 and its slow speed it really doesn't matter. You mean a CD4049 ?

I saw one guy build a complete CMOS processor board using 4000 series and god
knows what micro, probably running at ~ 1 MHz and it had about 3 decoupling
caps spread around. Now that DID have problems but the fucking clown who sold
it claimed that CMOS "didn't need decoupling" ! Jesus Wept. We liked the
product and offered to relayout the board for free so he could supply a
reliable model but he turned us down !

The company folded of course. Both supplier and customer.

Graham

 

[Eeyore]

ian field wrote:

Sometimes I've seen capacitor strips that can be cut to length, but never
did find a supplier.

RS ( Radiospares rswww.com ) and others do a socket with an integrated
decoupling cap. Costs an arm and a leg though !

But you don't need it for 4000 series. OTOH if it's a double sided board place
on the reverse side two traces from the power pins to the middle of the chip and
put an SMT cap there. But he is worrying about nothing.

Graham

 

[Eeyore]

Jamie wrote:

In our day we call them by pass cap's

You mean YOUR day and btw you don't use apostrophes for plurals.

and as far as i'm concerned, they still are.

NO. They're called DEcoupling caps as opposed to coupling caps. Because they do
DE opposite ! ;~)

Graham

 

[Eeyore]

Andrew Holme wrote:

"tempus fugit" <toccata@quitspammingme.ciaccess.com> wrote

do I use 1 cap for each IC? If so, (the ICs are fairly close together)
wouldn't the IC "see" the caps as being the paralleled value of the 3
caps,
thus reducing the available capacitance?

They're not like resistors. Parallel capacitance adds:

C1 || C2 || C3 = C1 + C2 + C3

Thank goodness this is the basics group ! I don't expect it'll be long
before we see graduates claiming the same though.

Graham

 

[Eeyore]

Tim Wescott wrote:

tempus fugit wrote:

I've got a circuit that uses 3 4049 inverters. On this IC, the V+ is on
pin 8 and the ground is on pin 1. I know that the decoupling caps need
to be as close to the IC as possible, but how can I connect 1 end of the
cap to V+ and the other to ground when the pins are so far away? Is it
sufficient to connect 1 end of the cap to V+ and the other to a nearby
ground node, or should the cap be connected close to the actual ground
pin of the IC? Also, do I use 1 cap for each IC? If so, (the ICs are
fairly close together) wouldn't the IC "see" the caps as being the
paralleled value of the 3 caps, thus reducing the available capacitance?
I was going to use 0.1uF for the value of each decoupling cap. Would it
also be wise to use a larger (1uF or higher) cap in parallel?

For that chip a 100nF (0.1u) ceramic up by pin 1, with a lead straight to
pin 1 and another one straight to pin 8 will be more than sufficient.

You can think about reducing them later -- but why? Unless you're trying
to shave deci-pennies off of the board cost, it's better to have too many
bypass caps than just enough.

Heck, I don't even always bother with one decoupling cap per chip with HC
logic !

Now consider a 40MHz '8051' with the power on pins 20 and 40 !

Graham

 

[Eeyore]

"David L. Jones" wrote:

"tempus fugit" wrote:

I've got a circuit that uses 3 4049 inverters. On this IC, the V+ is on pin
8 and the ground is on pin 1. I know that the decoupling caps need to be as
close to the IC as possible, but how can I connect 1 end of the cap to V+
and the other to ground when the pins are so far away?

There are many ways to do this depending on how your board and circuit
are layed out.

But it's 4000 series ! It's almost ANALOG !

In fact some analog circuits do use 4000 series.

Graham

 

[tempus fugit]

"Andrew Holme" <ah@nospam.co.uk> wrote in message
news:QQA3l.13783$wW1.3120@newsfe20.ams2...

"tempus fugit" <toccata@quitspammingme.ciaccess.com> wrote in message
news:1b084$494eb60b$d1d89b66$25834@PRIMUS.CA...
do I use 1 cap for each IC? If so, (the ICs are fairly close together)
wouldn't the IC "see" the caps as being the paralleled value of the 3
caps,
thus reducing the available capacitance?

They're not like resistors. Parallel capacitance adds:

C1 || C2 || C3 = C1 + C2 + C3

Duuuh....

Sorry, but I wasn't thinking - forgot they add up opposite to resistors.

Thanks for correcting me on that.

 

[IanM]

Tim Wescott wrote:

On Sun, 21 Dec 2008 16:33:47 -0500, tempus fugit wrote:

Hey all;

I've got a circuit that uses 3 4049 inverters. On this IC, the V+ is on
pin 8 and the ground is on pin 1. I know that the decoupling caps need
to be as close to the IC as possible, but how can I connect 1 end of the
cap to V+ and the other to ground when the pins are so far away? Is it
sufficient to connect 1 end of the cap to V+ and the other to a nearby
ground node, or should the cap be connected close to the actual ground
pin of the IC? Also, do I use 1 cap for each IC? If so, (the ICs are
fairly close together) wouldn't the IC "see" the caps as being the
paralleled value of the 3 caps, thus reducing the available capacitance?
I was going to use 0.1uF for the value of each decoupling cap. Would it
also be wise to use a larger (1uF or higher) cap in parallel?

Thanks

For that chip a 100nF (0.1u) ceramic up by pin 1, with a lead straight to
pin 1 and another one straight to pin 8 will be more than sufficient.

You can think about reducing them later -- but why? Unless you're trying
to shave deci-pennies off of the board cost, it's better to have too many
bypass caps than just enough.

Some general comments on effective grounding and decoupling pitched at

hobbyists (pros will know how much they can save by cutting back on
both, but for the rest of us, the small additional cost is easily repaid
by time saved debugging a glitchy circuit):

By ground, I and most other dabblers in low voltage electronics mean
chassis, common rail, 0V, battery negative, Logic negative supply etc,
NOT a hard wired connection to a copper stake in the earth.
Electricians are different - when they say ground, they mean ground!

If building on veroboard or solderless breadboard, make sure you have
reliable power and ground rails. Except in exceptional circumstances,
DONT wire them point to point. (low level audio is an exceptional
circumstance with special layout and decoupling requirements as are high
gain RF amplifiers and high power circuits in general.)

Most solderless breadboards have long rails of contact positions on each
edge, USE THEM (but beware of boards with a split between two halves of
the rail half way down it, they need a link inserted). Local decoupling
can be put over the top of critical ICs. Have an electrolytic capacitor
across the power rails where the power comes onto the board. Somewhere
between 10 and 100uF axial type is a good choice for most circuits on
breadboard.

If building digital or RF circuits on veroboard, you need a *solid*
ground rail. 2 or 3 tracks tied together at intervals along the board
is about right, or use the board crossways and run a heavy bare solid
copper buss wire along the top tacked down at intervals to any tracks
you want grounded by a little loop of bare wire over it, soldered
through two adjacent holes and to the copper buss wire.

Power rails can be done the same way but are usually less critical.
On veroboard, if you are using thin kynar wirewrap wire or similar for
your signal wires, DONT use it for power and ground.

All decoupling caps should lead as directly as possible to the ground
buss and to the + supply pin of the chip in question. 0.022uF to 0.1uF
disk or resin dipped ceramic capacitors are generally suitable for
individual chips. The chip should be located for the most direct ground
connection possible. If there is more length of wire than the width of
the board between the power supply and the board, put an electrolytic
(typically around 100x the individual ceramic capacitors) accross power
and ground where the supply wires go. Add an additional electrolytic
decoupling cap for every 10 chips.

The aim is to keep everything happily stable with respect to the ground
bus with any bounce from one IC switching *NOT* getting into other ones.

With some care with layout, bread boards are good for circuits operating
at up to a couple of MHz and veroboard up to a few tens of Mhz.

In the case of the OP's 4049 logic circuit, *ALL* 4000 series logic is
slow and low power so needs minimal decoupling. If there is no other
power consuming circuit on the board, a single 0.1uf ceramic located
centrally, WITH THE POWER SUPPLY WIRES CONNECTED DIRECTLY TO IT and as
short as possible supply and ground wires radiating to the three chips
will almost certainly be fine. If there are LEDs, a speaker or relay or
other high current loads, add an electrolytic capacitor as well.
However, I wouldn't build it that way unless I needed minimum size/weight.

If one is etching double sided PCBs or building complicated processor
boards etc., one is out of the 'dabbler' category, even if still an
amateur, so had better have a PROFESSIONAL understanding of layout
grounding and decoupling, othewise you will get PRO sised grief as
alluded to by Graham (Eeyore) in his first reply.

 

[Jamie]

Eeyore wrote:

Jamie wrote:


In our day we call them by pass cap's


You mean YOUR day and btw you don't use apostrophes for plurals.



and as far as i'm concerned, they still are.


NO. They're called DEcoupling caps as opposed to coupling caps. Because they do
DE opposite ! ;~)

Graham

Go fly a kite you little fairy..

You don't know the difference between the two, it's obvious.

--
http://webpages.charter.net/jamie_5"

 

[tempus fugit]

"IanM" <Invalid@totally.invalid> wrote in message
news:gioelo$qjh$1@energise.enta.net...

Tim Wescott wrote:
On Sun, 21 Dec 2008 16:33:47 -0500, tempus fugit wrote:

Hey all;

I've got a circuit that uses 3 4049 inverters. On this IC, the V+ is on
pin 8 and the ground is on pin 1. I know that the decoupling caps need
to be as close to the IC as possible, but how can I connect 1 end of
the
cap to V+ and the other to ground when the pins are so far away? Is it
sufficient to connect 1 end of the cap to V+ and the other to a nearby
ground node, or should the cap be connected close to the actual ground
pin of the IC? Also, do I use 1 cap for each IC? If so, (the ICs are
fairly close together) wouldn't the IC "see" the caps as being the
paralleled value of the 3 caps, thus reducing the available
capacitance?
I was going to use 0.1uF for the value of each decoupling cap. Would it
also be wise to use a larger (1uF or higher) cap in parallel?

Thanks

For that chip a 100nF (0.1u) ceramic up by pin 1, with a lead straight
to
pin 1 and another one straight to pin 8 will be more than sufficient.

You can think about reducing them later -- but why? Unless you're
trying
to shave deci-pennies off of the board cost, it's better to have too
many
bypass caps than just enough.

Some general comments on effective grounding and decoupling pitched at
hobbyists (pros will know how much they can save by cutting back on
both, but for the rest of us, the small additional cost is easily repaid
by time saved debugging a glitchy circuit):

By ground, I and most other dabblers in low voltage electronics mean
chassis, common rail, 0V, battery negative, Logic negative supply etc,
NOT a hard wired connection to a copper stake in the earth.
Electricians are different - when they say ground, they mean ground!

If building on veroboard or solderless breadboard, make sure you have
reliable power and ground rails. Except in exceptional circumstances,
DONT wire them point to point. (low level audio is an exceptional
circumstance with special layout and decoupling requirements as are high
gain RF amplifiers and high power circuits in general.)

Thanks for your reply Ian.

I am building on a non-etched board - one of those perfboards with little
copper pads you solder to (I assume this is the same as veroboard). What are
some of the special layout and decoupling requirements you mentioned in low
level audio circuits? I don't have any actual audio on this particular
board - it contains 3 voltage regulators (for 5, 9, and 12v) along with the
4049's in question, 2 8 bit latches, and a ULN2003 relay driver. The relays
are located on a separate board and switch audio signals from guitar fx
pedals in and out of the audio signal path.
Thanks

 

[whit3rd]

On Dec 22, 3:25 am, Eeyore <rabbitsfriendsandrelati...@hotmail.com>
wrote:

tempus fugit wrote:

I've got a circuit that uses 3 4049 inverters. ...the decoupling caps need to be as
close to the IC as possible

With a 4049 and its slow speed it really doesn't matter. You mean a CD4049 ?

I saw one guy build a complete CMOS processor board using 4000 series ...
Now that DID have problems but the fucking clown who sold
it claimed that CMOS "didn't need decoupling" !

Yes, that IS humorous. CMOS has good logic margins, it can tolerate
more noise than TTL, but it VERY MUCH needs decoupling.

The decoupling capacitors are required for the transient current
needs of the 4049; probably milliamps and sub-microsecond times,
so an inch of wire is not a real blockage (unless you use very fine
wire), either in terms of resistance or inductance. You need
wired-in decoupling within a couple of inches, but not within
millimeters.

It's not really 'slow speed' that matters, but the transient current
requirement. Fast ECL doesn't have any power-current change when
the state changes, and doesn't need much capacitance to decouple.
I've seen a chip (a self-clocking LED counter/driver in CMOS) with
nearly 100 mA spikes; it took LOTS more decoupling than usual
for that particular chip. This kind of problem occurs in CMOS when
a slow-slew-rate input signal is allowed, like in a mixed-signal
system.

Multilayer circuit boards are easier to decouple than random-wired
prototypes, because the ground/power layers are low inductance
conductors. The 'as close as possible' recommendation is
only a guide to prevent oscillatory feedback.

Catchphrase of the RF beginner:
"My amplifiers oscillate and my oscillators don't"