Decoding the content of a LFSR

K

Konx

Guest
Hi all!

Today, I'm facing a new problem.

I have a 4 bit LFSR counter. Then, I read out the content of the
registers and I need to decode (or better, to convert) this content to
the "real" value.

To do this in the testbench I used to simulate the logic, I was using
a function:

//4 bit decoding function
function [3:0] decode_4bits;
input [3:0] code;
reg [3:0] k;
reg [3:0] m;

begin
k[3:0] = 4'b1111;
m[3:0] = 4'b0000;

if(code[3:0]==4'b0000)
decode_4bits[3:0]=4'b1111; //impossible value = 15!

else
begin
while(code[3:0]!=k[3:0])
begin
k[3:0]= {k[1]^k[0],k[3:1]};
m[3:0]=m[3:0]+1;
end
decode_4bits[3:0]=m[3:0];
end
end
endfunction



The problem is this function cannot be synthesized because of the
while loop (for reference: I receive an error from Xilinx ISE: Xst:
1312 - Loop has iterated 64 times. Use "set -loop_iteration_limit XX"
to iterate more....I've tried to solve this problem in the way Xilin
suggest, but it doesn't work).

At the beginning I thought to change it in a for loop and use the
"break" instruction, but this command doesn't exist in Verilog (at
least, to obtain synthesizeable code).

I think that this problem should be quite common, but maybe I haven't
look in the right places...

thanks for any help

Francesco.
 
On Mon, 19 Apr 2010 07:07:05 -0700 (PDT), Konx <cescozep@gmail.com>
wrote:

Hi all!

Today, I'm facing a new problem.

I have a 4 bit LFSR counter. Then, I read out the content of the
registers and I need to decode (or better, to convert) this content to
the "real" value.

To do this in the testbench I used to simulate the logic, I was using
a function:

//4 bit decoding function
function [3:0] decode_4bits;
input [3:0] code;
reg [3:0] k;
reg [3:0] m;

begin
k[3:0] = 4'b1111;
m[3:0] = 4'b0000;

if(code[3:0]==4'b0000)
decode_4bits[3:0]=4'b1111; //impossible value = 15!

else
begin
while(code[3:0]!=k[3:0])
begin
k[3:0]= {k[1]^k[0],k[3:1]};
m[3:0]=m[3:0]+1;
end
decode_4bits[3:0]=m[3:0];
end
end
endfunction



The problem is this function cannot be synthesized because of the
while loop (for reference: I receive an error from Xilinx ISE: Xst:
1312 - Loop has iterated 64 times. Use "set -loop_iteration_limit XX"
to iterate more....I've tried to solve this problem in the way Xilin
suggest, but it doesn't work).

At the beginning I thought to change it in a for loop and use the
"break" instruction, but this command doesn't exist in Verilog (at
least, to obtain synthesizeable code).
Click to expand...
Why do you even need to break the loop? Out of the 16 possibilities
only one will work so just do all 16 without checking if you find the
result so a for loop which counts all the way through would work.
--
Muzaffer Kal

DSPIA INC.
ASIC/FPGA Design Services

http://www.dspia.com
 
On Mon, 19 Apr 2010 08:14:51 -0700 (PDT), Konx <cescozep@gmail.com>
wrote:

If I don't stop the loop, I just go through the complete sequence, and
then I have to compare the results: it is like using a table with all
the values, and compare the number_to_be_decoded with all the entries
of the table until I find the right one.

But this is what I want to avoid, because if we are talking about a 4
bit LFSR-counter I have only 15 states, but then I need to use the
same algorithm for a 8 bit and a 12 bit counter (and these two are too
big).

In the worst case, you have to count till the end (you might find what
Click to expand...
you're looking for in the last place you look ;-) and this being
hardware the size of logic will not increase or shrink based on where
it's found so you need all of the hardware anyway.

What I am suggesting is to record found and/or terminate increment
without terminating the loop ie:

if (a == b)
found = i;

which you can follow with

if (!found)
i = i + 1;

if you wish but it is unncessary extra logic. You'll find have only
one hit to your search so just record the value you find and let the
counter count which would give you the smallest area.
--
Muzaffer Kal

DSPIA INC.
ASIC/FPGA Design Services

http://www.dspia.com
 
On 19 Apr, 16:41, Muzaffer Kal <k...@dspia.com> wrote:

Why do you even need to break the loop? Out of the 16 possibilities
only one will work so just do all 16 without checking if you find the
result so a for loop which counts all the way through would work.
Click to expand...
Uhm...I'm not sure if I understand your point.

I try to explain from a different side the problem: the LFSR is
counting, and I put this number in a 4 bit array. Then, I need to say:
this number is 4 (for example).

With the while-loop I posted previously, what happens is that the for
loop go through all the couting until it matches the value in the LFSR
and while doing so, I'm using a binary counter to check how many
counts it takes. At the end, when the condition is met (so, when the
k[3:0] is equal to the number I pass to the function, code[3:0]) the
loop is stopped.

If I don't stop the loop, I just go through the complete sequence, and
then I have to compare the results: it is like using a table with all
the values, and compare the number_to_be_decoded with all the entries
of the table until I find the right one.

But this is what I want to avoid, because if we are talking about a 4
bit LFSR-counter I have only 15 states, but then I need to use the
same algorithm for a 8 bit and a 12 bit counter (and these two are too
big).

I hope I've clarified the problem.

If this was clear, please expand your explanation a bit :)

Thank you,

Francesco.
 
On 19 Apr, 18:33, Muzaffer Kal <k...@dspia.com> wrote:

[cut]

Thank you, your message give me a good hint!

Now, I'm trying this solution:

begin
for(i = 0; i<15; i=i+1)
begin
k[3:0]= {k[1]^k[0],k[3:1]};
m[3:0]=m[3:0]+1;

if(code[3:0] == k[3:0])
decode_4bits[3:0]=m[3:0];
end

So, what should happen is that I go through all the counting states,
and if one is equal to the value I pass, I record the value and give
it as the output of the function.

Thank you again!

Francesco.
 
On 21 Apr, 12:30, John_H <newsgr...@johnhandwork.com> wrote:
Just manually put together a case statement.
Click to expand...
Hi!

Well, this was the first (and simple) idea. The problem is that this
is quite simple for a 4-bit LFSR, but I have to decode a 8-bit and a
12-bit LFSR too...and in these cases it is a bit too much!

By the way, if someone of you knows of a program or a website that can
print all the possible state of a LFSR with given length and taps,
that would be really useful!

I know that I could write such a program by myself, but the point is
to debug my application, and having another application that I'm not
sure if it is correct is not the best way to do it :)

thanks

Francesco.
 
On Apr 21, 9:59 am, Konx <cesco...@gmail.com> wrote:
On 21 Apr, 12:30, John_H <newsgr...@johnhandwork.com> wrote:

Just manually put together a case statement.

Hi!

Well, this was the first (and simple) idea. The problem is that this
is quite simple for a 4-bit LFSR, but I have to decode a 8-bit and a
12-bit LFSR too...and in these cases it is a bit too much!

By the way, if someone of you knows of a program or a website that can
print all the possible state of a LFSR with given length and taps,
that would be really useful!

I know that I could write such a program by myself, but the point is
to debug my application, and having another application that I'm not
sure if it is correct is not the best way to do it :)

thanks

Francesco.
Click to expand...
For larger lookups you can use the LFSR to load a lookup table,
whether distributed CLB SelectRAM or BlockRAM. LFSR counts, binary
counter counts, LFSR is write address, binary value is write data.
One full count cycle and it's done. No room for error.

For generating LFSR values, I just use Excel. But for getting the
data into BlockRAM? Not my cup of tea.
 
On Apr 21, 7:44 pm, John_H <newsgr...@johnhandwork.com> wrote:
On Apr 21, 9:59 am, Konx <cesco...@gmail.com> wrote:



On 21 Apr, 12:30, John_H <newsgr...@johnhandwork.com> wrote:

Just manually put together a case statement.

Hi!

Well, this was the first (and simple) idea. The problem is that this
is quite simple for a 4-bit LFSR, but I have to decode a 8-bit and a
12-bit LFSR too...and in these cases it is a bit too much!

By the way, if someone of you knows of a program or a website that can
print all the possible state of a LFSR with given length and taps,
that would be really useful!

I know that I could write such a program by myself, but the point is
to debug my application, and having another application that I'm not
sure if it is correct is not the best way to do it :)

thanks

Francesco.

For larger lookups you can use the LFSR to load a lookup table,
whether distributed CLB SelectRAM or BlockRAM.  LFSR counts, binary
counter counts, LFSR is write address, binary value is write data.
One full count cycle and it's done.  No room for error.

For generating LFSR values, I just use Excel.  But for getting the
data into BlockRAM?  Not my cup of tea.
Click to expand...
In XST you can initialize an inferred memory using an initial
block. I know that this works with $readmemh, and I don't see
why it wouldn't work with the LFSR sequence logic in the block.
Why not just try it?

Regards,
Gabor
 
You must log in or register to reply here.

Welcome to EDABoard.com

Sponsor

Back
Top