Decoding multiple events

[DW]

Hi,
suppose I have two events which can occur and I want to control a common
register which depends on the event ordering, (so a single always block is
used). How can I decode the two events after they have occurred, so I know
which course of action to take. I have considered using two always blocks
but I'm not sure whether or not this would lead to unexpected behaviour.

e.g.

integer x;

always @ (negedge a or negedge b)
begin
...this is what I want but don't know how to do it:
if x = some value
if a negedge a occured then assign x = 1
otherwise (negedge b must have occured) assign x = 2
else if x = some other value
if a negedge a occured then assign x = 3
otherwise (negedge b must have occured) assign x = 4
end

Thanks for reading

 

[Jason Zheng]

I think this is what you want to say:

always @ (negedge a or negedge b)
if (~a) begin
if (x == value1) x <= 1;
else if (x == value2) x<= 3;
end
else if (~b) begin
if (x == value1) x <= 2;
else if (x == value2) x <= 4;
end

The exclusive cascading if statements should be sufficient to express
your concern about which event triggers. But it doesn't care about which
occurs first. To establish that kind of ordering, you would first have
to define something like a frame of time, where the ordering is clearly
defined. Think about this sequence: ... a b a a b a ..., which even
occurs first? The answer is ambiguous, unless you define a range of time
first. Hope that helps.

DW wrote:

Hi,
suppose I have two events which can occur and I want to control a common
register which depends on the event ordering, (so a single always block is
used). How can I decode the two events after they have occurred, so I know
which course of action to take. I have considered using two always blocks
but I'm not sure whether or not this would lead to unexpected behaviour.

e.g.

integer x;

always @ (negedge a or negedge b)
begin
...this is what I want but don't know how to do it:
if x = some value
if a negedge a occured then assign x = 1
otherwise (negedge b must have occured) assign x = 2
else if x = some other value
if a negedge a occured then assign x = 3
otherwise (negedge b must have occured) assign x = 4
end

Thanks for reading

 

[glen herrmannsfeldt]

DW wrote:

Hi,
suppose I have two events which can occur and I want to control a common
register which depends on the event ordering, (so a single always block is
used). How can I decode the two events after they have occurred, so I know
which course of action to take. I have considered using two always blocks
but I'm not sure whether or not this would lead to unexpected behaviour.

Assuming you are planning to synthesize this, consider some
what kind of logic you expect it to synthesize.

always @(negedge a)

likely synthesizes an edge triggered D type FF.

what does always @(negedge a or negedge b)

synthesize? Two DFF's? One DFF with an or gate on its input?

-- glen