decoder using generate statement

[Beginner_Verilog]

How can I construct a decoder Nx2^N using generate statement in
Verilog? Will case statement help?

 

[Jonathan Bromley]

On Sat, 24 Jan 2009 06:44:32 -0800 (PST), Beginner_Verilog wrote:

How can I construct a decoder Nx2^N using generate statement in
Verilog?

With excessive difficulty. I suspect you have a tiresome
prof who wants you to build the whole mess from 2-input
gates. If that's so, then don't expect too much help from
people here!

Will case statement help?

No, because case statements cannot be made generic;
their branches must be listed literally. You can't
use a parameter to alter the number of branches in
a case statement.

~~~~~~~~~~~~~~~~~~~

In general, don't reach for the generate construct as
a standard way to build things. There is in most cases
an easier way. How about this:

module decode_N_input
#(parameter N = 2)
( input wire [N-1 : 0] a
, input wire data
, output reg [(1<<N)-1 : 0] y
);

always @a begin
y = 0;
y[a] = data;
end

endmodule

Note the use of (1<<N) as a Verilog idiom for 2^N.
Verilog-2001 has the power operator ** but it returns
a real result in most situations, so the shift-left
formulation is better (it gives an integral result).

~~~~~~~~~~~~~~~~~~~~~~~~~

Afterthought: There IS a situation where generates
give you something you can't get any other way:
recursive instantiation. If you would like to
offer a description of a recursive architecture
for an N-input decoder, then I'll happily explain
how to use generates to implement it.
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
jonathan.bromley@MYCOMPANY.com
http://www.MYCOMPANY.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.

 

[Jonathan Bromley]

On Sat, 24 Jan 2009 16:38:55 +0000, Jonathan Bromley wrote:

always @a begin
y = 0;
y[a] = data;
end

Whoops. That should have been

always @* begin
...

or

always @(a or data) begin
...

Sorry.
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
jonathan.bromley@MYCOMPANY.com
http://www.MYCOMPANY.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.