declaring signals depending on generic parameters

[valentin tihomirov]

entity E is
SIZE: integer;
B : boolean;
end E;


The idea is to declare variable-length vector. Is wrapping the only solution
in VHDL?

architecture A of E is
signal S : std_logic_vector(B ? SIZE - 1: SIZE downto 0); -- C-like
ternary operators not supported

begin
...

 

[Jonathan Bromley]

"valentin tihomirov" <valentin_NOSPAM_NOWORMS@abelectron.com> wrote in
message news:c0vps9$1blik4$1@ID-212430.news.uni-berlin.de...

entity E is
SIZE: integer;
B : boolean;
end E;


The idea is to declare variable-length vector. Is wrapping the only
solution
in VHDL?

architecture A of E is
signal S : std_logic_vector(B ? SIZE - 1: SIZE downto 0); -- C-like
ternary operators not supported

Don't forget that you can use any function to initialise a constant.

I'm assuming that SIZE and B are generics. It would be crazy
if they were ports, of course.

architecture A of E is

function bit_extended_size(N: integer; B: boolean) return integer is
begin
if B then
return N-1;
else
return N;
end if;
end;

constant W : integer := bit_extended_size(SIZE, B);

signal S: std_logic_vector(W downto 0);

--

Jonathan Bromley, Consultant

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