A
ALuPin@web.de
Guest
Hi VHDL people,
I have declared the following global signals in a package:
TYPE typeRES_1920x1200 IS
RECORD
X : integer;
Y : integer;
HTOTAL : integer;
HFP : integer;
HST : integer;
HBP : integer;
VTOTAL : integer;
VFP : integer;
VST : integer;
VBP : integer;
END RECORD;
SIGNAL RES_1600x1200 : typeRES_1600x1200 1600,1200,2160,64,192,304,1250,1,3,46);
SIGNAL RES_XxY : typeRES_1920x1200 := (0,0,0,0,0,0,0,0,0,0);
In my main testbench (use showed package)
I make the following assignment:
process
begin
if condition=... then
RES_XxY <= RES_1600x1200;
end if;
wait until rising_edge(clock);
-- NOW I call a procedure which is declared in a separate
package
generate_dvi_frame (....);
wait;
end process,
In the procedure generate_dvi_frame I make the following assignments:
PROCEDURE generate_dvi_frame
( SIGNAL pClock : std_logic;
SIGNAL pHSyncPol : std_logic;
SIGNAL pVSyncPol : std_logic;
SIGNAL pOutScdt : OUT std_logic;
SIGNAL pOutDe : OUT std_logic;
SIGNAL pOutHSync : OUT std_logic;
SIGNAL pOutVSync : OUT std_logic) IS
CONSTANT X : integer := RES_XxY.X;
CONSTANT Y : integer := RES_XxY.Y;
CONSTANT HTOTAL : integer := RES_XxY.HTOTAL;
CONSTANT HFP : integer := RES_XxY.HFP;
CONSTANT HST : integer := RES_XxY.HST;
CONSTANT HBP : integer := RES_XxY.HBP;
CONSTANT VTOTAL : integer := RES_XxY.VTOTAL;
CONSTANT VFP : integer := RES_XxY.VFP;
CONSTANT VST : integer := RES_XxY.VST;
CONSTANT VBP : integer := RES_XxY.VBP;
.....
Is that possible / legal to assign signals to constants ?
I need the constants because I use loops in the procedure:
for j in 0 to Y loop
...
end loop;
Thank you for your opinion.
Rgds
André
I have declared the following global signals in a package:
TYPE typeRES_1920x1200 IS
RECORD
X : integer;
Y : integer;
HTOTAL : integer;
HFP : integer;
HST : integer;
HBP : integer;
VTOTAL : integer;
VFP : integer;
VST : integer;
VBP : integer;
END RECORD;
SIGNAL RES_1600x1200 : typeRES_1600x1200 1600,1200,2160,64,192,304,1250,1,3,46);
SIGNAL RES_XxY : typeRES_1920x1200 := (0,0,0,0,0,0,0,0,0,0);
In my main testbench (use showed package)
I make the following assignment:
process
begin
if condition=... then
RES_XxY <= RES_1600x1200;
end if;
wait until rising_edge(clock);
-- NOW I call a procedure which is declared in a separate
package
generate_dvi_frame (....);
wait;
end process,
In the procedure generate_dvi_frame I make the following assignments:
PROCEDURE generate_dvi_frame
( SIGNAL pClock : std_logic;
SIGNAL pHSyncPol : std_logic;
SIGNAL pVSyncPol : std_logic;
SIGNAL pOutScdt : OUT std_logic;
SIGNAL pOutDe : OUT std_logic;
SIGNAL pOutHSync : OUT std_logic;
SIGNAL pOutVSync : OUT std_logic) IS
CONSTANT X : integer := RES_XxY.X;
CONSTANT Y : integer := RES_XxY.Y;
CONSTANT HTOTAL : integer := RES_XxY.HTOTAL;
CONSTANT HFP : integer := RES_XxY.HFP;
CONSTANT HST : integer := RES_XxY.HST;
CONSTANT HBP : integer := RES_XxY.HBP;
CONSTANT VTOTAL : integer := RES_XxY.VTOTAL;
CONSTANT VFP : integer := RES_XxY.VFP;
CONSTANT VST : integer := RES_XxY.VST;
CONSTANT VBP : integer := RES_XxY.VBP;
.....
Is that possible / legal to assign signals to constants ?
I need the constants because I use loops in the procedure:
for j in 0 to Y loop
...
end loop;
Thank you for your opinion.
Rgds
André