Declaring an output as 'not connected'

[Joe]

When I instantiate a module and leave one of its output non connected,
I get a warning complaining that the output was left open (I am using
Xilinx ISE 8.1i).

Is there a way (or a trick) to declare in Verilog that a certain output
port is intentionally not connected? (and by that, avoiding the warning
message).

Thanks,

Joe

 

[unfrostedpoptart]

Joe wrote:

When I instantiate a module and leave one of its output non connected,
I get a warning complaining that the output was left open (I am using
Xilinx ISE 8.1i).

Is there a way (or a trick) to declare in Verilog that a certain output
port is intentionally not connected? (and by that, avoiding the warning
message).

This is tool-specific: there's no answer that will work with
everything. ISE, since 7.1, has had very extensive warning/error
filtering. Look at the docs to see how to use it.

David

 

Joe wrote:

When I instantiate a module and leave one of its output non connected,
I get a warning complaining that the output was left open (I am using
Xilinx ISE 8.1i).

Is there a way (or a trick) to declare in Verilog that a certain output
port is intentionally not connected? (and by that, avoiding the warning
message).

Thanks,

Joe

Reply : Ramakrishna
It is obvious that any simulater will flag a warning message if any of
the
o/p is kept open(i.e., output is floating).

You have an option for filtering the Messages. for example: if you are
using
ncverilog as a simulator then you need to pass the filter constraint
throgh the
Command line like +nowarn< argument >, here argument is the header of
the
meassge (warning).

ok,
bye
RK