Declare before use, or vice-versa?

[Evan Lavelle]

Does anyone know what exactly can be referenced before declaration?
The LRM seems pretty vague on this. As far as I can see, it only says
that

- specparams must be declared before use
- events must be declared before use
- UDPs may be instantiated before declaration

Presumably the full list of use-before-declare objects are modules and
UDPs, although I think some tools also add explicitly-declared module
inputs to this list.

Thanks -

Evan

 

[Jonathan Bromley]

On Wed, 09 May 2007 17:48:39 +0100, Evan Lavelle <nospam@nospam.com>
wrote:

Does anyone know what exactly can be referenced before declaration?
The LRM seems pretty vague on this. As far as I can see, it only says
that

- specparams must be declared before use
- events must be declared before use
- UDPs may be instantiated before declaration

Presumably the full list of use-before-declare objects are modules and
UDPs, although I think some tools also add explicitly-declared module
inputs to this list.

Subprograms can be used before declaration, although the
reasoning behind that is kinda weird - IIRC a call to an
as-yet undeclared function or task is treated as a cross-module
reference and the name is resolved at elaboration time.
This is because you can use an unqualified (non-dotted) name
to call functions or tasks in an enclosing (parent) module
instance. However, at elab time, if the name turns out
to be that of a task/function declared later in the current
module, it's the local one that you get.

Is it completely unfair to ask why you're working on a
Verilog parser?
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
jonathan.bromley@MYCOMPANY.com
http://www.MYCOMPANY.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.

 

[Jonathan Bromley]

On Wed, 09 May 2007 18:09:08 +0100, Jonathan Bromley
<jonathan.bromley@MYCOMPANY.com> wrote:

On Wed, 09 May 2007 17:48:39 +0100, Evan Lavelle <nospam@nospam.com
wrote:

Does anyone know what exactly can be referenced before declaration?

Subprograms can be used before declaration

True, but what I *forgot* to add was...

With the two exceptions of module/UDP names and task/function
names, anything that will go out-of-module must be specified
as a dotted name. And I'm fairly sure this means that any
name must be declared before use unless it falls into one
of those categories.

Don't forget implicit wire declaration on port connection :-(
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
jonathan.bromley@MYCOMPANY.com
http://www.MYCOMPANY.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.

 

[Evan Lavelle]

On Wed, 09 May 2007 18:09:08 +0100, Jonathan Bromley
<jonathan.bromley@MYCOMPANY.com> wrote:

Thanks; I'd missed subprograms.

Is it completely unfair to ask why you're working on a
Verilog parser?

Displacement activity; resting between engagements

Evan

 

[Stephen Williams]

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Evan Lavelle wrote:

On Wed, 09 May 2007 18:09:08 +0100, Jonathan Bromley
jonathan.bromley@MYCOMPANY.com> wrote:

Thanks; I'd missed subprograms.

Is it completely unfair to ask why you're working on a
Verilog parser?

Displacement activity; resting between engagements

Somebody quick give this guy a job before he codes some more!-)

- --
Steve Williams "The woods are lovely, dark and deep.
steve at icarus.com But I have promises to keep,
http://www.icarus.com and lines to code before I sleep,
http://www.picturel.com And lines to code before I sleep."
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