declaration and initialization inside initial block

[Nikhil]

Hi
Is it possible in verilog(or verilog 2001) to declare and
initialize a register inside a initial block .
Nikhil

 

[John_H]

Declarations are always outside of procedural blocks.
You could set the default type (Verilog2001 feature - check your tool for
info) to reg and the first reference in the initial block without a
declaration would effectively declare it.
Alternatively, the initial assignment could be made at the register
declaration where there is no initial block.

reg [11:0] MyReg = 12'head;

My simulator recognizes this last form so I've used it here and there in my
test bench. Synthesis is a different problem. Few synthesis tools support
initial values at *all* though this seems to be changing (slowly) in the
FPGA world for the devices where the initial states *can* be arbitrarily
defined when the device is configured.


"Nikhil" <nikhilkj2000@yahoo.com> wrote in message
news:709ece6b.0411010732.1e57d552@posting.google.com...

Hi
Is it possible in verilog(or verilog 2001) to declare and
initialize a register inside a initial block .
Nikhil

 

[Steven Sharp]

Stephen Williams <spamtrap@icarus.com> wrote in message news:<5336b$41866bcb$40695902$8315@msgid.meganewsservers.com>...

John_H wrote:
Declarations are always outside of procedural blocks.

Actually, that's not true.

initial begin :name_block
reg [11:0] MyReg = 12'head;
... other stuff...;
end

But a declaration inside a named block cannot have an
initial value. This was a deliberate restriction to
avoid user misunderstanding. It might appear that the
variable would be re-initialized every time that execution
entered the scope, when in fact it would only be initialized
once at the start of simulation.

So this example is illegal.