Decimation filter using verilog

Ok I have looked at the other posts but to no success. I was wondering
if anyone could help me with this prgram basically it is decimating
the filtered output every 64 samples. I have the filter working ok but
the decimation(marked as average) is not working properly. Could
anyone spot any errors to me or help please


//Filter
module averagefilter( rst, clk, filter_input, av_out);

input clk, rst;
input[7:0] filter_input;
//reg [7:0]filter_input;
//output[7:0] filter_out;
reg [7:0] Z1,Z2;
reg [7:0] window[63:0];
reg [7:0]a;
reg [6:0]i;
output[7:0] av_out;
//output control;
//reg control;
reg[7:0] filter_out, av_out;

//This is the filter part of our code.

// This takes in the data
always @ (posedge clk or negedge rst)
begin
//Making the Reset an active High
if (rst == 1'b1)
begin

//Setting Z1 and Z2 states
Z1 <= filter_input;
Z2 <= Z1;

filter_out <= {2'b00,filter_input[7:2]} + {2'b00,Z1[7:2]} +
{1'b0,Z2[7:1]};
//Right bit shifting in order to divide the binary number
by 4
//Z2 is right bit shifted so that the binary number is
divided by a half


end

else
//Default: Setting the previous states values to zero
begin
Z1 <= 8'b0;
Z2 <= 8'b0;
end

end



//Average Module







always @ (posedge clk or negedge rst)
//need to have the reset and default values set
if (rst == 1'b1)

repeat(64)
begin
window <= filter_out;
a <= (a + window);

// control<=0;
if(i==63)
begin
av_out <= (a>>6);
// control=1;
end
i=i+1;
end


endmodule

 

[gabor]

On Nov 27, 7:51 am, mairead.ly...@gmail.com wrote:

Ok I have looked at the other posts but to no success. I was wondering
if anyone could help me with this prgram basically it is decimating
the filtered output every 64 samples. I have the filter working ok but
the decimation(marked as average) is not working properly. Could
anyone spot any errors to me or help please

//Filter
module averagefilter( rst, clk, filter_input, av_out);

input clk, rst;
input[7:0] filter_input;
//reg [7:0]filter_input;
//output[7:0] filter_out;
reg [7:0] Z1,Z2;
reg [7:0] window[63:0];
reg [7:0]a;
reg [6:0]i;
output[7:0] av_out;
//output control;
//reg control;
reg[7:0] filter_out, av_out;

//This is the filter part of our code.

// This takes in the data
always @ (posedge clk or negedge rst)
begin
   //Making the Reset an active High
If you want this to synthesize with an active high reset,

you also need to change negedge to posedge in the sensitivity
list.

  if (rst == 1'b1)
          begin

          //Setting Z1 and Z2 states
          Z1 <= filter_input;
          Z2 <= Z1;

           filter_out <= {2'b00,filter_input[7:2]} + {2'b00,Z1[7:2]} +
{1'b0,Z2[7:1]};
            //Right bit shifting in order to divide the binary number
by 4
            //Z2 is right bit shifted so that the binary number is
divided by a half

           end

  else
           //Default: Setting the previous states values to zero
           begin
           Z1 <= 8'b0;
           Z2 <= 8'b0;
end

end

//Average Module

always @ (posedge clk or negedge rst)
//need to have the reset and default values set
if (rst == 1'b1)

I'm not sure whether repeat is valid for synthesis, but

in any case what do you expect "i" to do during
the 64 iterations? What is its value when you
start the loop? What is the value of "a" at the
start of the loop for that matter?
Furthermore the non-blocking
assigns to "a" will all queue up and only the last of the
64 "wins", so you won't really do a sum here.

I'd suggest using a "for" loop if you want to add 64
items together in one clock cycle. In synthesis,
however this will make a very large adder tree and
could run very slow as a result. Also you need to
use blocking assigns to get a sum rather than
simply a + window [63] (assuming you initialize
a and i to zero).

repeat(64)
begin
  window <= filter_out;
  a <= (a + window);

//  control<=0;
 if(i==63)
 begin
   av_out <= (a>>6);
// control=1;
  end
 i=i+1;
end

endmodule

Good luck,
Gabor