decimation clock

Hi,

If I have to decimate by 10.

Is it better to create a second clock2=1/10 clock1 from a counter
or
in the second stage working at clock2, make work this part on clock1
in multi-cycle

always@(posedge clock1)
if (reset)
....
else
if (count=9)
design to work at clk2
end
end

or

always @posedge clock2
if (reset)
....
else
design working at clk2
end

I guess it is safety to use all on clock1 domain, easier for the
synthesis tool...
We don't have to take care of te delay between clock1 and clock2
generated with clock1

Thanks

 

[hairyotter]

Hi,

it all depends on the amount of logic you have on the two clock
domains.

If you're clocking at the fast clock the logic that needs to run on
the slow one, you're basically burning 10 times the power.

There are ways to reduce that. There are tools (both rtl and
synthesis) that will help you, provided you write your rtl properly.

On the other hand, having two clocks and keeping them aligned in a big
chip adds significant complication.

On an fpga it might actually make sense to create a slow clock, the
power advantage will be winning.

On an asic, you might want to create two clocks and treat them
asynchronously, if the bulk of your logic runs on the slow one.

Marco.

 

[gabor]

On Apr 14, 1:18 am, hairyotter <marco.br...@gmail.com> wrote:

Hi,

it all depends on the amount of logic you have on the two clock
domains.

If you're clocking at the fast clock the logic that needs to run on
the slow one, you're basically burning 10 times the power.

This really depends on the technology. In a Xilinx FPGA
for example, adding more loads to the same global clock
has minimal power implications. The devices using the
clock enable would still be switching at the reduced
speed so the overall power demand is pretty much a wash.

For an ASIC, however I would agree that this is a power
issue.

There are ways to reduce that. There are tools (both rtl and
synthesis) that will help you, provided you write your rtl properly.

On the other hand, having two clocks and keeping them aligned in a big
chip adds significant complication.

On an fpga it might actually make sense to create a slow clock, the
power advantage will be winning.

On an asic, you might want to create two clocks and treat them
asynchronously, if the bulk of your logic runs on the slow one.

Marco.