Decimal to binary for comparison

[Klaus Thiele]

Hi

I have a simple question. I have a 16-bit register that stores me the
information about the usage of 16 registers. If a bit is set the
register is locked else its free to use. Next, I read then in a value
that wants to use one of the registers. The value is a decimal number
between 0 and 15, so I wonder if VHDL offers an easy way to convert from
decimal to binary so that I can compare then values with an AND mask.
This the thing should also be sythesizable on an XIlinx FPGA

Thanks,
Klaus

 

[Mike Treseler]

Klaus Thiele wrote:

The value is a decimal number
between 0 and 15, so I wonder if VHDL offers an easy way to convert from
decimal to binary so that I can compare then values with an AND mask.
This the thing should also be sythesizable on an XIlinx FPGA

I would declare that natural range as a subtype
and use a constant or variable of that subtype
for the comparison. Synthesis will work out
the details.

-- Mike Treseler

 

[Klaus Thiele]

Probably what you're trying to say is that you've got a number in the
range 0 to 15 (most likely represented inside the FPGA as a 4 bit
binary number) and you want to decode to select one of 16 different
things. In that case, Google for 4->16 decoders, de-multiplexers,
etc. You'll likely implement something like this...

process
begin
Select_This <= (others => '0');
Select_This(Index) <= '1'
end process;

Yes, that it is what I am looking for! A 4->16 decoder

 

[Klaus Thiele]

process
begin
Select_This <= (others => '0');
Select_This(Index) <= '1'
end process;

that looks like a nice one

process (A, E)
begin
if (E='0') then
D <= "0000000000000000";
else
case A is
when "0000" =>
D <= "0000000000000001";
when "0001" =>
D <= "0000000000000010";
when "0010" =>
D <= "0000000000000100";
when "0011" =>
D <= "0000000000001000";
when "0100" =>
D <= "0000000000010000";
when "0101" =>
D <= "0000000000100000";
when "0110" =>
D <= "0000000001000000";
when "0111" =>
D <= "0000000010000000";
when "1000" =>
D <= "0000000100000000";
when "1001" =>
D <= "0000001000000000";
when "1010" =>
D <= "0000010000000000";
when "1011" =>
D <= "0000100000000000";
when "1100" =>
D <= "0001000000000000";
when "1101" =>
D <= "0010000000000000";
when "1110" =>
D <= "0100000000000000";
when "1111" =>
D <= "1000000000000000";
when others =>
D <= "0000000000000000";
end case;
end if;
end process;
end Behavioral;

http://toolbox.xilinx.com/docsan/xilinx5/data/docs/lib/lib0126_110.html

 

[KJ]

On May 23, 11:20 am, Klaus Thiele <Thiel...@gmx.de> wrote:

Hi

I have a simple question. I have a 16-bit register that stores me the
information about the usage of 16 registers. If a bit is set the
register is locked else its free to use. Next, I read then in a value
that wants to use one of the registers. The value is a decimal number
between 0 and 15, so I wonder if VHDL offers an easy way to convert from
decimal to binary so that I can compare then values with an AND mask.
This the thing should also be sythesizable on an XIlinx FPGA

Perhaps you should go back and rethink your question. Inside an FPGA
you only have binary logic, there is no decimal so the number you
'read in' will not be decimal.

Probably what you're trying to say is that you've got a number in the
range 0 to 15 (most likely represented inside the FPGA as a 4 bit
binary number) and you want to decode to select one of 16 different
things. In that case, Google for 4->16 decoders, de-multiplexers,
etc. You'll likely implement something like this...

process
begin
Select_This <= (others => '0');
Select_This(Index) <= '1'
end process;