M
mnentwig
Guest
Hi,
I'm looking for a vendor-independent solution to configure RAM contents o
an FPGA without rebuilding the RTL. Is there such a thing?
Xilinx has their proprietary data2mem interface that let me replace data i
the bitstream file, but it requires a lot of "low-level" work to describ
how the RAM is formed from primitives. What I'm looking for is a generi
solution, in the same way as putting initial values into inferred RAM, bu
without having to recompile everything.
I've built my own "homespun" loader using a hardware UART interface, i.e
some FTDI breakout board, and it works well enough within its limitation
(extra gates, possibility of bus contention with the design). Now I wa
wondering, as this seems like such a common problem, is there any know
"simple" way for this? JTAG maybe? I did some superficial search here bu
JTAG seemed to get quite complex, if I stay away from vendor-dependen
tools.
---------------------------------------
Posted through http://www.FPGARelated.com
I'm looking for a vendor-independent solution to configure RAM contents o
an FPGA without rebuilding the RTL. Is there such a thing?
Xilinx has their proprietary data2mem interface that let me replace data i
the bitstream file, but it requires a lot of "low-level" work to describ
how the RAM is formed from primitives. What I'm looking for is a generi
solution, in the same way as putting initial values into inferred RAM, bu
without having to recompile everything.
I've built my own "homespun" loader using a hardware UART interface, i.e
some FTDI breakout board, and it works well enough within its limitation
(extra gates, possibility of bus contention with the design). Now I wa
wondering, as this seems like such a common problem, is there any know
"simple" way for this? JTAG maybe? I did some superficial search here bu
JTAG seemed to get quite complex, if I stay away from vendor-dependen
tools.
---------------------------------------
Posted through http://www.FPGARelated.com