J
John Larkin
Guest
https://www.dropbox.com/s/1xx7sz1e5rg6jsi/JLDDS_100M_4K.jpg?raw=1
https://www.dropbox.com/s/3859sc4qayv3jva/JLDDS_100M_4K_A.asc?dl=0
It would have been a horror to build a digital phase accumulator in LT
Spice, so I did it with the bootstrapped sample-and-hold. 1 LSB is 1
volt, making a 4 kilovolt sawtooth. Close enough.
We\'ll probably do this in a cute little efinix FPGA (digitally, and
not 4KV) which has a megabit of ram, so we can pull more bits out of
the phase accumulator and have a lot more entries in the sine table,
which will improve jitter at low frequencies.
We might even use a 14-bit DAC, if that helps much. The efinix RAM
comes in slices 5 bits wide, so 14 takes no more than 12. Might
explore 10 and see what happens.
Now I need a good way to measure peroid jitter, so I can play with
options.
keywords LT Spice DDS clock frequency synthesizer phase accumulator
jitter filter coffee yardwork sucks
https://www.dropbox.com/s/3859sc4qayv3jva/JLDDS_100M_4K_A.asc?dl=0
It would have been a horror to build a digital phase accumulator in LT
Spice, so I did it with the bootstrapped sample-and-hold. 1 LSB is 1
volt, making a 4 kilovolt sawtooth. Close enough.
We\'ll probably do this in a cute little efinix FPGA (digitally, and
not 4KV) which has a megabit of ram, so we can pull more bits out of
the phase accumulator and have a lot more entries in the sine table,
which will improve jitter at low frequencies.
We might even use a 14-bit DAC, if that helps much. The efinix RAM
comes in slices 5 bits wide, so 14 takes no more than 12. Might
explore 10 and see what happens.
Now I need a good way to measure peroid jitter, so I can play with
options.
keywords LT Spice DDS clock frequency synthesizer phase accumulator
jitter filter coffee yardwork sucks