DDS-Based PLL

K

Kevin Neilson

Guest
An alternative using a conventional VCO-based PLL with an FPGA would be to
implement most of the PLL as a DDS. The FPGA would have a phase accumulator
and BRAM-based sine LUT and would output a sine to a cheap 8-bit DAC. The
output of the DAC would be reconstructed with a simple lowpass (with a
simplicity based on the oversampling rate) and then squared with a
comparator to make a clock of any desired frequency. The comparator would
do the job of placing the edge of the clock at the correct interpolated
point between DAC samples. This has several advantages. You can synthesize
any clock with any crazy multiplication ratio without fractional-N
techniques. You can dither or spread the clock easily and digitally control
overshoot when transitioning. You get rid of a bunch of analog hardware,
including a VCO and a loop filter and charge pump, all of which have varying
characteristics from part to part. You could even generate really fast
clocks by bandpassing one of the DAC's images. Yet I rarely see this
technique used. Is is just that it's used more than I think, or does it
have some disadvantage like introducing a lot of phase noise?
-Kevin
 
Analog Devices has a whole line of parts based on integrating the whole ball
of wax.

The technique is used, just not in the boards *we've* seen.

One of the issues is that the bulk of designs don't need a precise,
arbitrary, low jitter clock source opting instead for lower cost, fixed (or
limited) solutions.

If you have a clock that's low enough in frequency to use a really cheap
DAC, you could get better results by using the MSB output of a faster DDS.
If you're fast enough to need a decent DAC, it'll cost you. A simple
lowpass filter works fine for some apps but may involve a less-simple filter
than you expect to block out an alias as close as the 3rd harmonic.
Oversampling is great but increases the cost of the DAC further. The Analog
Devices chips integrate most of these functions in one device providing
exceptional spectral purity.

I put together a DDS based synthesizer that adds controlled levels of
sinusoidal jitter about 6 years ago and have since watched some of the
offerings that provide higher integration.

The higher frequency extraction with a bandpass can work but the filtering
is easier with single-sideband modulation of a high frequency carrier with a
DDS controlled offset. I/Q modulation devices achieve this translation
(with -35 dBc images) and are used significantly in wireless systems and
don't have the narrow bandwidth, high rejection requirements of picking out,
say, the ninth harmonic. Good I/Q is cheap stuff nowadays.


"Kevin Neilson" <kevin_neilson@removethiscomcast.net> wrote in message
news:Zahfc.37136$wP1.140239@attbi_s54...
An alternative using a conventional VCO-based PLL with an FPGA would be to
implement most of the PLL as a DDS. The FPGA would have a phase
accumulator
and BRAM-based sine LUT and would output a sine to a cheap 8-bit DAC. The
output of the DAC would be reconstructed with a simple lowpass (with a
simplicity based on the oversampling rate) and then squared with a
comparator to make a clock of any desired frequency. The comparator would
do the job of placing the edge of the clock at the correct interpolated
point between DAC samples. This has several advantages. You can
synthesize
any clock with any crazy multiplication ratio without fractional-N
techniques. You can dither or spread the clock easily and digitally
control
overshoot when transitioning. You get rid of a bunch of analog hardware,
including a VCO and a loop filter and charge pump, all of which have
varying
characteristics from part to part. You could even generate really fast
clocks by bandpassing one of the DAC's images. Yet I rarely see this
technique used. Is is just that it's used more than I think, or does it
have some disadvantage like introducing a lot of phase noise?
-Kevin
Click to expand...
 
Fine frequency resolution with reasonably low jitter.

I just finished and tested an FPGA design using a 30-bit DDS phase
accumulator that is conservatively clocked at 80 MHz and, with the help of a
DCM in Frequency Synthesis mode and a binary divider chain, generates any
frequency from 1 Hz to 80 MHz with 1 Hz granularity.
The output period jitter is <300 picoseconds peak-to-peak.
There is a roadmap to increase the output frequency to max 5 GHz at
substantially reduced jitter.

Peter Alfke
From: "John_H" <johnhandwork@mail.com
Organization: Xerox Officeprinting NewsReader Service
Reply-To: "John_H" <johnhandwork@mail.com
Newsgroups: comp.arch.fpga
Date: Wed, 14 Apr 2004 21:00:54 GMT
Subject: Re: DDS-Based PLL

Analog Devices has a whole line of parts based on integrating the whole ball
of wax.

The technique is used, just not in the boards *we've* seen.

One of the issues is that the bulk of designs don't need a precise,
arbitrary, low jitter clock source opting instead for lower cost, fixed (or
limited) solutions.

If you have a clock that's low enough in frequency to use a really cheap
DAC, you could get better results by using the MSB output of a faster DDS.
If you're fast enough to need a decent DAC, it'll cost you. A simple
lowpass filter works fine for some apps but may involve a less-simple filter
than you expect to block out an alias as close as the 3rd harmonic.
Oversampling is great but increases the cost of the DAC further. The Analog
Devices chips integrate most of these functions in one device providing
exceptional spectral purity.

I put together a DDS based synthesizer that adds controlled levels of
sinusoidal jitter about 6 years ago and have since watched some of the
offerings that provide higher integration.

The higher frequency extraction with a bandpass can work but the filtering
is easier with single-sideband modulation of a high frequency carrier with a
DDS controlled offset. I/Q modulation devices achieve this translation
(with -35 dBc images) and are used significantly in wireless systems and
don't have the narrow bandwidth, high rejection requirements of picking out,
say, the ninth harmonic. Good I/Q is cheap stuff nowadays.


"Kevin Neilson" <kevin_neilson@removethiscomcast.net> wrote in message
news:Zahfc.37136$wP1.140239@attbi_s54...
An alternative using a conventional VCO-based PLL with an FPGA would be to
implement most of the PLL as a DDS. The FPGA would have a phase
accumulator
and BRAM-based sine LUT and would output a sine to a cheap 8-bit DAC. The
output of the DAC would be reconstructed with a simple lowpass (with a
simplicity based on the oversampling rate) and then squared with a
comparator to make a clock of any desired frequency. The comparator would
do the job of placing the edge of the clock at the correct interpolated
point between DAC samples. This has several advantages. You can
synthesize
any clock with any crazy multiplication ratio without fractional-N
techniques. You can dither or spread the clock easily and digitally
control
overshoot when transitioning. You get rid of a bunch of analog hardware,
including a VCO and a loop filter and charge pump, all of which have
varying
characteristics from part to part. You could even generate really fast
clocks by bandpassing one of the DAC's images. Yet I rarely see this
technique used. Is is just that it's used more than I think, or does it
have some disadvantage like introducing a lot of phase noise?
-Kevin
Click to expand...
 
Peter,
I'd like to know more about this. If the output of a phase accumulator has
300ps jitter, then that indicates that the phase accumulator clock is at
least 3.3GHz. How would you ever get speeds like that in a Xilinx?
-Kevin

"Peter Alfke" <peter@xilinx.com> wrote in message
news:BCA312C6.5ED9%peter@xilinx.com...
Fine frequency resolution with reasonably low jitter.

I just finished and tested an FPGA design using a 30-bit DDS phase
accumulator that is conservatively clocked at 80 MHz and, with the help of
a
DCM in Frequency Synthesis mode and a binary divider chain, generates any
frequency from 1 Hz to 80 MHz with 1 Hz granularity.
The output period jitter is <300 picoseconds peak-to-peak.
There is a roadmap to increase the output frequency to max 5 GHz at
substantially reduced jitter.

Peter Alfke
From: "John_H" <johnhandwork@mail.com
Organization: Xerox Officeprinting NewsReader Service
Reply-To: "John_H" <johnhandwork@mail.com
Newsgroups: comp.arch.fpga
Date: Wed, 14 Apr 2004 21:00:54 GMT
Subject: Re: DDS-Based PLL

Analog Devices has a whole line of parts based on integrating the whole
ball
of wax.

The technique is used, just not in the boards *we've* seen.

One of the issues is that the bulk of designs don't need a precise,
arbitrary, low jitter clock source opting instead for lower cost, fixed
(or
limited) solutions.

If you have a clock that's low enough in frequency to use a really cheap
DAC, you could get better results by using the MSB output of a faster
DDS.
If you're fast enough to need a decent DAC, it'll cost you. A simple
lowpass filter works fine for some apps but may involve a less-simple
filter
than you expect to block out an alias as close as the 3rd harmonic.
Oversampling is great but increases the cost of the DAC further. The
Analog
Devices chips integrate most of these functions in one device providing
exceptional spectral purity.

I put together a DDS based synthesizer that adds controlled levels of
sinusoidal jitter about 6 years ago and have since watched some of the
offerings that provide higher integration.

The higher frequency extraction with a bandpass can work but the
filtering
is easier with single-sideband modulation of a high frequency carrier
with a
DDS controlled offset. I/Q modulation devices achieve this translation
(with -35 dBc images) and are used significantly in wireless systems and
don't have the narrow bandwidth, high rejection requirements of picking
out,
say, the ninth harmonic. Good I/Q is cheap stuff nowadays.


"Kevin Neilson" <kevin_neilson@removethiscomcast.net> wrote in message
news:Zahfc.37136$wP1.140239@attbi_s54...
An alternative using a conventional VCO-based PLL with an FPGA would be
to
implement most of the PLL as a DDS. The FPGA would have a phase
accumulator
and BRAM-based sine LUT and would output a sine to a cheap 8-bit DAC.
The
output of the DAC would be reconstructed with a simple lowpass (with a
simplicity based on the oversampling rate) and then squared with a
comparator to make a clock of any desired frequency. The comparator
would
do the job of placing the edge of the clock at the correct interpolated
point between DAC samples. This has several advantages. You can
synthesize
any clock with any crazy multiplication ratio without fractional-N
techniques. You can dither or spread the clock easily and digitally
control
overshoot when transitioning. You get rid of a bunch of analog
hardware,
including a VCO and a loop filter and charge pump, all of which have
varying
characteristics from part to part. You could even generate really fast
clocks by bandpassing one of the DAC's images. Yet I rarely see this
technique used. Is is just that it's used more than I think, or does
it
have some disadvantage like introducing a lot of phase noise?
-Kevin
Click to expand...
 
On Thu, 15 Apr 2004 05:51:10 GMT, "Kevin Neilson"
<kevin_neilson@removethiscomcast.net> wrote:

Peter,
I'd like to know more about this. If the output of a phase accumulator has
300ps jitter, then that indicates that the phase accumulator clock is at
least 3.3GHz. How would you ever get speeds like that in a Xilinx?
-Kevin
Click to expand...
An ability to position an edge within 300ps does not imply that a
3+GHz clock has been used. It is possible to use multiple phases of a
lower frequency clock to achieve the same thing.

Regards,
Allan.
 
An ability to position an edge within 300ps does not imply that a
3+GHz clock has been used. It is possible to use multiple phases of a
lower frequency clock to achieve the same thing.
Click to expand...
Or an adjustable delay. Consider the MC100E195
http://www.onsemi.com/pub/Collateral/MC10E195-D.PDF
It claims 20 ps resolution. (Mainly for ATE equipment, I think.)

I've always wanted to build something that could use one of them.

I'd guess Peter is using the equivalent thing packaged in a DCM

--
The suespammers.org mail server is located in California. So are all my
other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited
commercial e-mail to my suespammers.org address or any of my other addresses.
These are my opinions, not necessarily my employer's. I hate spam.
 
Kevin Neilson wrote:

An alternative using a conventional VCO-based PLL with an FPGA would be to
implement most of the PLL as a DDS.
Click to expand...
Not really.
First the frequency has to be PLL'ed up. A DDS just makes a frequency
lower, much lower usually. Some of the more expensive Analog devices
DDS have selectable PLLs.

Rene
--
Ing.Buero R.Tschaggelar - http://www.ibrtses.com
& commercial newsgroups - http://www.talkto.net
 
"Rene Tschaggelar" <none@none.net> wrote in message
news:407ec586$0$713$5402220f@news.sunrise.ch...
Kevin Neilson wrote:

An alternative using a conventional VCO-based PLL with an FPGA would be
to
implement most of the PLL as a DDS.

Not really.
Click to expand...
??

If you read his full post, you would have noted that the selection of a high
frequency alias from the DDS output was part of the ideas he was asking
about. Very valid.

Also, not all VCO-based systems result in higher frequency values.

My suggestion of using sin/cos DDS outputs to drive an I/Q modulator doesn't
require a VCO.

Not really.
 
"Hal Murray" <hmurray@suespammers.org> wrote in message
news:107sm91nneuiv61@corp.supernews.com...
An ability to position an edge within 300ps does not imply that a
3+GHz clock has been used. It is possible to use multiple phases of a
lower frequency clock to achieve the same thing.

Or an adjustable delay. Consider the MC100E195
http://www.onsemi.com/pub/Collateral/MC10E195-D.PDF
It claims 20 ps resolution. (Mainly for ATE equipment, I think.)

I've always wanted to build something that could use one of them.

I'd guess Peter is using the equivalent thing packaged in a DCM

--
Click to expand...
These statements are both true but assume one can wield great control over
the DCM, which I don't think is possible. There is no direct access to the
taps on a DCM or the tap mux, and the only way to change the tap is by using
the phase increment function, which allows you to increment or decrement one
tap only, and also very very slowly. It's meant to be used infrequently.
Mabye Peter has some backdoor access to the DCM we don't know about.

You can use carry chain muxes to get 200ps resolution, but it's hard to get
the routing from the outputs to have deterministic delays.
-Kevin
 
The applications I was thinking of mostly is sampling clocks for ADCs or
DACs, so having low jitter is important and in that case using the MSB of a
DDS wouldn't suffice. I had one application in which I had to generate a
DAC clock that wasn't really large but was a really strange multiple of an
input clock (the ratio was close to 80000/78000, irreducable) and PLLs
couldn't handle that ratio and even if they could the comparison frequency
would be really low and the loop filter cutoff would have had to be really
small.

I like the offset idea. Of course that means you need an accurate
high-frequency source with which to mix; I guess that would be generated
with a PLL.
-Kevin

"John_H" <johnhandwork@mail.com> wrote in message
news:aEhfc.10$6Z6.289@news-west.eli.net...
Analog Devices has a whole line of parts based on integrating the whole
ball
of wax.

The technique is used, just not in the boards *we've* seen.

One of the issues is that the bulk of designs don't need a precise,
arbitrary, low jitter clock source opting instead for lower cost, fixed
(or
limited) solutions.

If you have a clock that's low enough in frequency to use a really cheap
DAC, you could get better results by using the MSB output of a faster DDS.
If you're fast enough to need a decent DAC, it'll cost you. A simple
lowpass filter works fine for some apps but may involve a less-simple
filter
than you expect to block out an alias as close as the 3rd harmonic.
Oversampling is great but increases the cost of the DAC further. The
Analog
Devices chips integrate most of these functions in one device providing
exceptional spectral purity.

I put together a DDS based synthesizer that adds controlled levels of
sinusoidal jitter about 6 years ago and have since watched some of the
offerings that provide higher integration.

The higher frequency extraction with a bandpass can work but the filtering
is easier with single-sideband modulation of a high frequency carrier with
a
DDS controlled offset. I/Q modulation devices achieve this translation
(with -35 dBc images) and are used significantly in wireless systems and
don't have the narrow bandwidth, high rejection requirements of picking
out,
say, the ninth harmonic. Good I/Q is cheap stuff nowadays.


"Kevin Neilson" <kevin_neilson@removethiscomcast.net> wrote in message
news:Zahfc.37136$wP1.140239@attbi_s54...
An alternative using a conventional VCO-based PLL with an FPGA would be
to
implement most of the PLL as a DDS. The FPGA would have a phase
accumulator
and BRAM-based sine LUT and would output a sine to a cheap 8-bit DAC.
The
output of the DAC would be reconstructed with a simple lowpass (with a
simplicity based on the oversampling rate) and then squared with a
comparator to make a clock of any desired frequency. The comparator
would
do the job of placing the edge of the clock at the correct interpolated
point between DAC samples. This has several advantages. You can
synthesize
any clock with any crazy multiplication ratio without fractional-N
techniques. You can dither or spread the clock easily and digitally
control
overshoot when transitioning. You get rid of a bunch of analog
hardware,
including a VCO and a loop filter and charge pump, all of which have
varying
characteristics from part to part. You could even generate really fast
clocks by bandpassing one of the DAC's images. Yet I rarely see this
technique used. Is is just that it's used more than I think, or does it
have some disadvantage like introducing a lot of phase noise?
-Kevin
Click to expand...
 
"Kevin Neilson" <kevin_neilson@removethiscomcast.net> wrote in message
news:eHVfc.145675$gA5.1776343@attbi_s03...
The applications I was thinking of mostly is sampling clocks for ADCs or
DACs, so having low jitter is important and in that case using the MSB of
a
DDS wouldn't suffice. I had one application in which I had to generate a
DAC clock that wasn't really large but was a really strange multiple of an
input clock (the ratio was close to 80000/78000, irreducable) and PLLs
couldn't handle that ratio and even if they could the comparison frequency
would be really low and the loop filter cutoff would have had to be really
small.

I like the offset idea. Of course that means you need an accurate
high-frequency source with which to mix; I guess that would be generated
with a PLL.
-Kevin
Click to expand...

The jitter associated with *most* digital-based clocking techniques is tough
to deal with for ADC and DAC systems without the PLL and VCO. What *can* be
done to get the irreducably low frequency to not cripple your system is to
not go so low.... Fractional-N synthesizers can give superb spectral
results with non-integer divides. In some cases, these Fractional-N devices
which "dither" the divider before the phase comparator can produce close-in
harmonics that aren't reasonable to filter. With arbitrary numerator and
denominator values (producing an odd modulus in the accumulator) these
close-in sidebands can be pushed out to well beyond the PLL's loop filter
cutoff. With sigma-delta techniques in some of the commercially available
Fractional-N synthesizers, some problem sidebands can be squashed. Neat
stuff, all of it.

- John_H
 
Peter Alfke wrote:
Fine frequency resolution with reasonably low jitter.

I just finished and tested an FPGA design using a 30-bit DDS phase
accumulator that is conservatively clocked at 80 MHz and, with the help of a
DCM in Frequency Synthesis mode and a binary divider chain, generates any
frequency from 1 Hz to 80 MHz with 1 Hz granularity.
The output period jitter is <300 picoseconds peak-to-peak.
There is a roadmap to increase the output frequency to max 5 GHz at
substantially reduced jitter.
Click to expand...
Seems there's a lot packed into a few sentences here - when/where can
we see more info ?
-jg
 
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