V
valtih1978
Guest
I read on termination topics and they say that having Vtt equal to the
high-to-low transition level is a bad idea (tristated buses will
noise-switch all the readers and, thus, consume unnecessary power). Yet,
JEDEC prescribes using 1.25 Vtt for DDR, based on 2.5 volt SSTL_2
signaling. Why?
high-to-low transition level is a bad idea (tristated buses will
noise-switch all the readers and, thus, consume unnecessary power). Yet,
JEDEC prescribes using 1.25 Vtt for DDR, based on 2.5 volt SSTL_2
signaling. Why?