A
ALuPin
Guest
Hi,
I have a question concerning the write operation for a DDR SDRAM with
a burst
length of 1:
If you have a look at
http://mitglied.lycos.de/vazquez78
you can see the sequence of eight back-to-back write requests that go
to two different rows in the DDR SDRAM device. In the shown instance
(DDR
SDRAM Controller MegaCore User Guide Altera) the burst length is one
on the Controller Local Interface and two on the Memory Side.
My question:
Why do the addresses on the local interface "local_col_addr"
"020","021","022","023","030","031","032","033"
turn to the memory addresses
"0040","0042","0044","0046","0060","0062","0064","0066" on the DDR
SDRAM Interface ?
It is said later in the User Guide that the controller runs the DQ
port to
the DDR devices at one half the width and twice the rate of the DATAIN
port (input data at the local interface of the controller).
But how are the coherence with the shown example addresses?
Thank you in advance.
Rgds
André
I have a question concerning the write operation for a DDR SDRAM with
a burst
length of 1:
If you have a look at
http://mitglied.lycos.de/vazquez78
you can see the sequence of eight back-to-back write requests that go
to two different rows in the DDR SDRAM device. In the shown instance
(DDR
SDRAM Controller MegaCore User Guide Altera) the burst length is one
on the Controller Local Interface and two on the Memory Side.
My question:
Why do the addresses on the local interface "local_col_addr"
"020","021","022","023","030","031","032","033"
turn to the memory addresses
"0040","0042","0044","0046","0060","0062","0064","0066" on the DDR
SDRAM Interface ?
It is said later in the User Guide that the controller runs the DQ
port to
the DDR devices at one half the width and twice the rate of the DATAIN
port (input data at the local interface of the controller).
But how are the coherence with the shown example addresses?
Thank you in advance.
Rgds
André