DDR/SDR-SDRAM Bank Switching Doubt

[Abdul K Shaik]

Hi All,

In a DDR - SDRAM or in SDR - SDRAM with a single device(not DIMM)

is the following Command sequence is valid?

Assuming 4 BANK DRAM, Burst Length = 8, Sequential
Can a WRITE/READ command be issued to an alternate bank (B), while the
Bank A is PRECHARGING?
if this valid then will there be any gaps on DQ bus for READ/WRITE
operations.

i.e is it possible to issue read/write to keep the DQ bus always
occupied with data without any dead/overhead cycles.?
Is it possible to have the DQ bus with read/write data while one of
the BANK is precharing.?

is it possible to completely hide the over head of opening the row and
closing a row in a particular bank with open/close of an another
row/bank while keeping the DQ bus always busy with data.?

Can WRITE B/READ B follow a PRECHARGE A without meeting the row
precharge time for BANK A?

Any info. on DDR/SDR SDRAM bank switching will help.

Thanking you in Advace.

Regards,
Abdul

 

[David Jones]

In article <95cb0937.0308081601.23f5fa9e@posting.google.com>,
Abdul K Shaik <sabdulk@yahoo.com> wrote:

Hi All,

In a DDR - SDRAM or in SDR - SDRAM with a single device(not DIMM)

is the following Command sequence is valid?

Assuming 4 BANK DRAM, Burst Length = 8, Sequential
Can a WRITE/READ command be issued to an alternate bank (B), while the
Bank A is PRECHARGING?

Yes.

if this valid then will there be any gaps on DQ bus for READ/WRITE
operations.

Depends on the timing.

i.e is it possible to issue read/write to keep the DQ bus always
occupied with data without any dead/overhead cycles.?

Yes.

Is it possible to have the DQ bus with read/write data while one of
the BANK is precharing.?

is it possible to completely hide the over head of opening the row and
closing a row in a particular bank with open/close of an another
row/bank while keeping the DQ bus always busy with data.?

All ways of asking the same thing. Yes and yes.

Can WRITE B/READ B follow a PRECHARGE A without meeting the row
precharge time for BANK A?

If you are doing a burst of 8, then it's pretty hard to not meet.

If you are doing a read burst of 2, then it's also hard to not meet, due to
CAS latency.

If you are doing a write burst of 2 to an open bank then it could be possible
to get that off within the precharge time of bank A, which is typically
2-3 clocks.

Any info. on DDR/SDR SDRAM bank switching will help.

The JEDEC spec is available for download at www.jedec.org. You will need
to register with login ID and password, but this won't cost you anything.