DDR/SDR-SDRAM Bank Switching Doubt

[Abdul K Shaik]

Hi All,

In a DDR - SDRAM or in SDR - SDRAM with a single device(not DIMM)

is the following Command sequence is valid?

Assuming 4 BANK DRAM, Burst Length = 8, Sequential
Can a WRITE/READ command be issued to an alternate bank (B), while the
Bank A is PRECHARGING?
if this valid then will there be any gaps on DQ bus for READ/WRITE
operations.

i.e is it possible to issue read/write to keep the DQ bus always
occupied with data without any dead/overhead cycles.?
Is it possible to have the DQ bus with read/write data while one of
the BANK is precharing.?

is it possible to completely hide the over head of opening the row and
closing a row in a particular bank with open/close of an another
row/bank while keeping the DQ bus always busy with data.?

Can WRITE B/READ B follow a PRECHARGE A without meeting the row
precharge time for BANK A?

Any info. on DDR/SDR SDRAM bank switching will help.

Thanking you in Advace.

Regards,
Abdul

 

[Prasanna]

sabdulk@yahoo.com (Abdul K Shaik) wrote in message news:<95cb0937.0308081602.369a413b@posting.google.com>...

Hi All,

In a DDR - SDRAM or in SDR - SDRAM with a single device(not DIMM)

is the following Command sequence is valid?

Assuming 4 BANK DRAM, Burst Length = 8, Sequential
Can a WRITE/READ command be issued to an alternate bank (B), while the
Bank A is PRECHARGING?
if this valid then will there be any gaps on DQ bus for READ/WRITE
operations.

i.e is it possible to issue read/write to keep the DQ bus always
occupied with data without any dead/overhead cycles.?
Is it possible to have the DQ bus with read/write data while one of
the BANK is precharing.?

is it possible to completely hide the over head of opening the row and
closing a row in a particular bank with open/close of an another
row/bank while keeping the DQ bus always busy with data.?

Can WRITE B/READ B follow a PRECHARGE A without meeting the row
precharge time for BANK A?

Any info. on DDR/SDR SDRAM bank switching will help.

Thanking you in Advace.

Regards,
Abdul

Hi,

When you refer to the memory model, you will notice that there are
timing diagrams for single and multi bank accesses. If you look into
the timing parameters such as Tcas, Trbd (Irbd) along with burst
length (BL), they tell you whether your data will appear continous or
not.

For ex :

CL = 2, BL = 4 may do a continous data burst.
CL = 3, BL = 2 may leave data gaps.

You can check memory datasheet to find out if there is hidden
pre-charge and how to take best advantage of the same.

- Prasanna

 

[b1hghm62 M1L4R4]

fgfgh
"Abdul K Shaik" <sabdulk@yahoo.com> wrote in message
news:95cb0937.0308081602.369a413b@posting.google.com...

Hi All,

In a DDR - SDRAM or in SDR - SDRAM with a single device(not DIMM)

is the following Command sequence is valid?

Assuming 4 BANK DRAM, Burst Length = 8, Sequential
Can a WRITE/READ command be issued to an alternate bank (B), while the
Bank A is PRECHARGING?
if this valid then will there be any gaps on DQ bus for READ/WRITE
operations.

i.e is it possible to issue read/write to keep the DQ bus always
occupied with data without any dead/overhead cycles.?
Is it possible to have the DQ bus with read/write data while one of
the BANK is precharing.?

is it possible to completely hide the over head of opening the row and
closing a row in a particular bank with open/close of an another
row/bank while keeping the DQ bus always busy with data.?

Can WRITE B/READ B follow a PRECHARGE A without meeting the row
precharge time for BANK A?

Any info. on DDR/SDR SDRAM bank switching will help.

Thanking you in Advace.

Regards,
Abdul

 

[Samitinjoy Pal]

Comments below:

b1hghm62 M1L4R4 wrote:

fgfgh
"Abdul K Shaik" <sabdulk@yahoo.com> wrote in message
news:95cb0937.0308081602.369a413b@posting.google.com...

Hi All,

In a DDR - SDRAM or in SDR - SDRAM with a single device(not DIMM)

is the following Command sequence is valid?

Assuming 4 BANK DRAM, Burst Length = 8, Sequential
Can a WRITE/READ command be issued to an alternate bank (B), while the
Bank A is PRECHARGING?
if this valid then will there be any gaps on DQ bus for READ/WRITE
operations.
YES it is possible.

i.e is it possible to issue read/write to keep the DQ bus always
occupied with data without any dead/overhead cycles.?
Is it possible to have the DQ bus with read/write data while one of
the BANK is precharing.?

YES it is possible. U would hit dead cycles during refresh though.
is it possible to completely hide the over head of opening the row and
closing a row in a particular bank with open/close of an another
row/bank while keeping the DQ bus always busy with data.?

YES it is possible.
Can WRITE B/READ B follow a PRECHARGE A without meeting the row
precharge time for BANK A?
No. You can't violate tras min timing

Any info. on DDR/SDR SDRAM bank switching will help.

Thanking you in Advace.

Regards,
Abdul



Samit