S
Sylvain Munaut
Guest
Hi,
I'd like to design a small board with a Spartan 3 and some Dynamic RAM memory.
Since I'd like not to be limited by memory bandwith, I was thinking to use DDR.
However I'm not an exepert in High speed board design and don't have big tool to simulate my board signal integrity, cross talk, ...
I've seen some "amateur" (in the good sense of the term) board with SDRAM and simple SDRAM controller in VHDL. However for DDR, not much.
So I'd like to know if it's possible to do one that would be clocked at 100Mhz DDR ( 200Mhz ) 32 bits, without eating 2000 slice of my FPGA for the DDR controller ... I'm willing to give about 500 slices for it.
Of course, I've seen Xilinx app notes, but they say to simulate it all with IBIS models and I have no clue ... So just by doing a careful routing of signals ( ensure same length for all signals, preferably short, with minimum vias ), should it be possible ? Any advice ?
Thanks,
Sylvain Munaut
I'd like to design a small board with a Spartan 3 and some Dynamic RAM memory.
Since I'd like not to be limited by memory bandwith, I was thinking to use DDR.
However I'm not an exepert in High speed board design and don't have big tool to simulate my board signal integrity, cross talk, ...
I've seen some "amateur" (in the good sense of the term) board with SDRAM and simple SDRAM controller in VHDL. However for DDR, not much.
So I'd like to know if it's possible to do one that would be clocked at 100Mhz DDR ( 200Mhz ) 32 bits, without eating 2000 slice of my FPGA for the DDR controller ... I'm willing to give about 500 slices for it.
Of course, I've seen Xilinx app notes, but they say to simulate it all with IBIS models and I have no clue ... So just by doing a careful routing of signals ( ensure same length for all signals, preferably short, with minimum vias ), should it be possible ? Any advice ?
Thanks,
Sylvain Munaut