DDR Lines on FPGA : Physical considerations

[Sylvain Munaut]

Hi,

Follow up to a preceding post, I finally decided to use DDR : 2 chips of 16bits wide to have 32bits bus.

Since I got access to a ibis simulator thru a friend, I did a few simulation.


For the shared lines (like clk & address), I used :

Spartan3 DDR Chips
output Input
|\ _______ ________ |\
| >------O_______)------O________)-----| >-
|/ | |/
|
| |\
'-----------------| >-
|/


For the not shared lines ( like data ):

Spartan3 DDR Chips
output Input
|\ _______ |\
| >------O_______)-------| >-
|/ |/



The lines between the spartan3 and DDR are between 2 and 4 inch. I'm trying to get them as short as possible, I haven't done yet the layout and it's just a worst case estimate.

I simulated with a 100Mhz square wave, and (for my inexperienced eyes), it looked awful !
The square wave is FAR from anything close to square or monotonic, 1V undershoot and overshoot.

So I tried to add a series resistor at the output of spartan 3 output. 35 ohm seemed like a good value but it's more try & test than a real computed values ( track impedance is 70 ohm, at least that's what the simulation tool tells me ).

Also, I used the LVCMOS_25 standard, with Slow and Fast and multiple drive strenght. The Fast 16ma seems the best.

But that's for Spartan -> DDR. For bidir lines, should I put R or R/2 series resistor at each end ?
If I decide to use the DCI of Spartan 3 for series termination, the resistor is placed at the output of the output buffer but not at the input of the input buffer, so I suppose it's even better.

I haven't simulated the DDR -> Spartan 3 direction because my tool don't seen to recognize the output driver description in Micron's IBIS models, I still have to investigate this.


I'm not sure of my simulations but they look good. Do the results sounds ok ? Any advice ?

Thanks for any clue or insight you may have. Making such a board is not quite cheap and I can't afford to have to redesign it multiples times, I'd like the first one to work



Sylvain

 

[John_H]

I'd suggest looking at the results with the series resistor at the S3 driver
before the transmission line for a baseline and then moved to the end of the
transmission line before the split for a comparison. You may see very
little difference, suggesting the location of the resistor isn't critical;
but then you might see it is. In motherboards, the series resistors are
often at the edge of the DDR connector, not as close to the driver as
possible.

Having a series resistor at your input shouldn't affect your timing much
(such as for bidir lines); at that point the only delay seen is the RC for
the series resistor and the input parasitics. For example, 35 ohm and 8 pF
gives a 280 ps time constant which is small for the overall timing budget in
the slower DDR implementation.

The biggest suggestion I have is to keep the DDR-side stubs to a minimum,
reducing the problems introduced by the impedance mismatch.


"Sylvain Munaut" <tnt_at_246tNt_dot_com@reducespam.com> wrote in message
news:411a7baf$0$285$ba620e4c@news.skynet.be...

Hi,

Follow up to a preceding post, I finally decided to use DDR : 2 chips of
16bits wide to have 32bits bus.

Since I got access to a ibis simulator thru a friend, I did a few
simulation.


For the shared lines (like clk & address), I used :

Spartan3 DDR Chips
output Input
|\ _______ ________ |\
| >------O_______)------O________)-----| >-
|/ | |/
|
| |\
'-----------------| >-
|/


For the not shared lines ( like data ):

Spartan3 DDR Chips
output Input
|\ _______ |\
| >------O_______)-------| >-
|/ |/



The lines between the spartan3 and DDR are between 2 and 4 inch. I'm
trying to get them as short as possible, I haven't done yet the layout and

it's just a worst case estimate.

I simulated with a 100Mhz square wave, and (for my inexperienced eyes), it
looked awful !
The square wave is FAR from anything close to square or monotonic, 1V
undershoot and overshoot.

So I tried to add a series resistor at the output of spartan 3 output. 35
ohm seemed like a good value but it's more try & test than a real computed

values ( track impedance is 70 ohm, at least that's what the simulation tool
tells me ).

Also, I used the LVCMOS_25 standard, with Slow and Fast and multiple drive
strenght. The Fast 16ma seems the best.

But that's for Spartan -> DDR. For bidir lines, should I put R or R/2
series resistor at each end ?
If I decide to use the DCI of Spartan 3 for series termination, the
resistor is placed at the output of the output buffer but not at the input

of the input buffer, so I suppose it's even better.

I haven't simulated the DDR -> Spartan 3 direction because my tool don't
seen to recognize the output driver description in Micron's IBIS models, I

still have to investigate this.

I'm not sure of my simulations but they look good. Do the results sounds
ok ? Any advice ?

Thanks for any clue or insight you may have. Making such a board is not
quite cheap and I can't afford to have to redesign it multiples times, I'd

like the first one to work

Sylvain

 

[Steven K. Knapp]

Just in case you haven't already seen it, I would recommend taking a look at
the Spartan-3 133 MHz DDR SDRAM reference design that supports up to DDR266
(PC2100) . Much of the engineering effort is already done.

The application note and reference design is on the Xilinx Memory Corner.
http://www.xilinx.com/memory

http://www.xilinx.com/products/design_resources/mem_corner/resource/xaw_dram_ddr.htm

You'll want "XAPP768c: 133 MHz DDR Interface for Spartan-3 HDL Code". The
application note and reference design are available to registered Xilinx web
site viewers (which is a PITA, but unfortunately, that's the policy).

Another recommendation is to take a look at the following overview
application note. This one is available without registering.

XAPP802: Memory Interface Application Notes Overview
http://www.xilinx.com/bvdocs/appnotes/xapp802.pdf

Also, depending on the specific memory device you are using, you probably
want to use one of the SSTL I/O standards. Likewise, some of the Micron
devices, and probably others, have SSTL_2, Class II output buffers and offer
a reduced drive strength option for low load or point-to-point designs.
---------------------------------
Steven K. Knapp
Applications Manager, Xilinx Inc.
General Products Division
Spartan-3/II/IIE FPGAs
http://www.xilinx.com/spartan3
---------------------------------
Spartan-3: Make it Your ASIC



"Sylvain Munaut" <tnt_at_246tNt_dot_com@reducespam.com> wrote in message
news:411a7baf$0$285$ba620e4c@news.skynet.be...

Hi,

Follow up to a preceding post, I finally decided to use DDR : 2 chips of
16bits wide to have 32bits bus.

Since I got access to a ibis simulator thru a friend, I did a few
simulation.


For the shared lines (like clk & address), I used :

Spartan3 DDR Chips
output Input
|\ _______ ________ |\
| >------O_______)------O________)-----| >-
|/ | |/
|
| |\
'-----------------| >-
|/


For the not shared lines ( like data ):

Spartan3 DDR Chips
output Input
|\ _______ |\
| >------O_______)-------| >-
|/ |/



The lines between the spartan3 and DDR are between 2 and 4 inch. I'm
trying to get them as short as possible, I haven't done yet the layout and

it's just a worst case estimate.

I simulated with a 100Mhz square wave, and (for my inexperienced eyes), it
looked awful !
The square wave is FAR from anything close to square or monotonic, 1V
undershoot and overshoot.

So I tried to add a series resistor at the output of spartan 3 output. 35
ohm seemed like a good value but it's more try & test than a real computed

values ( track impedance is 70 ohm, at least that's what the simulation tool
tells me ).

Also, I used the LVCMOS_25 standard, with Slow and Fast and multiple drive
strenght. The Fast 16ma seems the best.

But that's for Spartan -> DDR. For bidir lines, should I put R or R/2
series resistor at each end ?
If I decide to use the DCI of Spartan 3 for series termination, the
resistor is placed at the output of the output buffer but not at the input

of the input buffer, so I suppose it's even better.

I haven't simulated the DDR -> Spartan 3 direction because my tool don't
seen to recognize the output driver description in Micron's IBIS models, I

still have to investigate this.

I'm not sure of my simulations but they look good. Do the results sounds
ok ? Any advice ?

Thanks for any clue or insight you may have. Making such a board is not
quite cheap and I can't afford to have to redesign it multiples times, I'd

like the first one to work

Sylvain

 

[Sylvain Munaut]

John_H wrote:

I'd suggest looking at the results with the series resistor at the S3 driver
before the transmission line for a baseline and then moved to the end of the
transmission line before the split for a comparison. You may see very
little difference, suggesting the location of the resistor isn't critical;
but then you might see it is. In motherboards, the series resistors are
often at the edge of the DDR connector, not as close to the driver as
possible.

Looking at the results that doesn't change much the appearence of the signals or the delay.

Having a series resistor at your input shouldn't affect your timing much
(such as for bidir lines); at that point the only delay seen is the RC for
the series resistor and the input parasitics. For example, 35 ohm and 8 pF
gives a 280 ps time constant which is small for the overall timing budget in
the slower DDR implementation.

Yes, I'm planning on slow DDR (100Mhz), so that doesn't seem to have much impact.

The biggest suggestion I have is to keep the DDR-side stubs to a minimum,
reducing the problems introduced by the impedance mismatch.

Ok, given that the DDR chips are very close to the FPGA, the resitors might in fact be at the same distance from FPGA than the DDR chips.



Sylvain

 

[Sylvain Munaut]

Steven K. Knapp wrote:

Just in case you haven't already seen it, I would recommend taking a look at
the Spartan-3 133 MHz DDR SDRAM reference design that supports up to DDR266
(PC2100) . Much of the engineering effort is already done.

The application note and reference design is on the Xilinx Memory Corner.
http://www.xilinx.com/memory

http://www.xilinx.com/products/design_resources/mem_corner/resource/xaw_dram_ddr.htm

You'll want "XAPP768c: 133 MHz DDR Interface for Spartan-3 HDL Code". The
application note and reference design are available to registered Xilinx web
site viewers (which is a PITA, but unfortunately, that's the policy).

I had a look at some application notes from Xilinx of course. But I didn't saw that one. I'm waiting for approbation from the "memory team".
The ones I looked at had no mention of terminations, only considerations about trace lenght/delay. (Or I missed them). I just saw on a Virtex2 userguide and in SelectI/O app note that for SSTL_2 and DDR, they use a pull resistor of 50 ohm to Vtt=1.25v at both ends with a series of 25ohm.
But that seem complicated, probably not needed for slow DDR and that will draw significantly more current than a simple series termination.

In a Micron app note, then they only use a 60 ohm series resitor at the middle of point to point connection.

Another recommendation is to take a look at the following overview
application note. This one is available without registering.

XAPP802: Memory Interface Application Notes Overview
http://www.xilinx.com/bvdocs/appnotes/xapp802.pdf

Not much informations about signal integrity there.

Also, depending on the specific memory device you are using, you probably
want to use one of the SSTL I/O standards. Likewise, some of the Micron
devices, and probably others, have SSTL_2, Class II output buffers and offer
a reduced drive strength option for low load or point-to-point designs.

Yes, they indeed uses SSTL_2 (Micron's chips)



Thanks for the suggestions,

Sylvain Munaut