DDR design needs a little help

[DanK]

Hopefully some nice DDR guru is out there...

My DDR design is for a single REGISTERED DDR modules (64 bits wide plus
ECC/parity bits). The module was acting like cas latency was 2.5 when I had
set it to 2, so I changed my design to work with CL=2.5 and continued with
the de-bug. Now I'm pretty sure the module thinks the burst length is set
to 4, even though I set it to 2. (a 128 bit write to address 0/1 also gets
written into address 2/3). I've gone over the initialization and I can't
find anything wrong. Anybody got any ideas?

Thanks

Dan

 

[PeteS]

DanK wrote:

Hopefully some nice DDR guru is out there...

My DDR design is for a single REGISTERED DDR modules (64 bits wide plus
ECC/parity bits). The module was acting like cas latency was 2.5 when I had
set it to 2, so I changed my design to work with CL=2.5 and continued with
the de-bug. Now I'm pretty sure the module thinks the burst length is set
to 4, even though I set it to 2. (a 128 bit write to address 0/1 also gets
written into address 2/3). I've gone over the initialization and I can't
find anything wrong. Anybody got any ideas?

Thanks

Dan

You don't say whether you are using someone else's DDR controller or
are making your own.

There are many adjustable parameters in a typical DDR controller (and
in the DDR device - there are two accessible registers - status and
extended status).

Apart from the multiple writes, what other issues (faults) do you see?

Cheers

PeteS