DDC design

[Jan]

Hi,

Can anyone point me at a vhdl design for a DDC, Digital Down Convertor,
in an FPGA. Preferably free.
It should be a wideband design with up to 10MHz and as low as 100KHz
bandwidth. Resolution of adc is 14bits.
Also it should be possible to synthesise it with the Xilinx Webpack.

Thanks for any help

Jan

 

[MM]

There is a free DDC Xilinx core that comes with the ISE tools (not sure
about Webpack). It is not a VHDL design though...

/Mikhail



"Jan" <jan_marijnisse@hotmail.com> wrote in message
news:bjvdln$nsb$1@news3.tilbu1.nb.home.nl...

Hi,

Can anyone point me at a vhdl design for a DDC, Digital Down Convertor,
in an FPGA. Preferably free.
It should be a wideband design with up to 10MHz and as low as 100KHz
bandwidth. Resolution of adc is 14bits.
Also it should be possible to synthesise it with the Xilinx Webpack.

Thanks for any help

Jan