DCM problem with a SPARTAN-3 from xilinx: large range of clo

P

Pieter

Guest
Hi,

I hope anybody can solve my problem, i tried all many things to solve
it.
I've got the following problem:
In a vhdl design i implemented a DCM to make sure that a clock signal
is always 50% duty cycle at the output, so I thought that this would
be the easiest with a DCM, because it has an built in duty cycle
correction.
The major problem is that the input clock is variable between 40MHz
and 160MHz,
because I is used in an PC monitor with DVI input.
So everytime the frequency chances I will reset the DCM, at first I
worked very well
but sometime the output clock is not the same as the input clock. To
solve this I
wrote some code that counts some pulse from the incoming and the
outgoing clock.
Than I compare the two counters, if the difference is not so much
(between 1 or 5) then
the output is ok. This solve already a big problem that I had with the
DCM.
But now I see that sometimes the input and the output clock are
sometimes
not in phase and because of this I get now image on the screen or it
is wrong. You've got to "reload"
the signal and then the image appears or is it corrected. I already
tried to also reset
with the locked signal, but then I really don't works or is may clock
output from the DCM very strange.

A smaller thing, how higher the clock input is how smaller the output
signal comes, so at 160MHz
is maybe 500Mv from min to max. This stays the same if I change to the
HIGH mode.

Hope that someone nows how to solve it, of have a small tip for me
that would be very welcome
Thanks already

Greets
Pieter
 
On Oct 24, 9:08 pm, Pieter <pieter.huy...@gmail.com> wrote:
Hi,

I hope anybody can solve my problem, i tried all many things to solve
it.
I've got the following problem:
In a vhdl design i implemented a DCM to make sure that a clock signal
is always 50% duty cycle at the output, so I thought that this would
be the easiest with a DCM, because it has an built in duty cycle
correction.
The major problem is that the input clock is variable between 40MHz
and 160MHz,
because I is used in an PC monitor with DVI input.
So everytime the frequency chances I will reset the DCM, at first I
worked very well
but sometime the output clock is not the same as the input clock. To
solve this I
wrote some code that counts some pulse from the incoming and the
outgoing clock.
Than I compare the two counters, if the difference is not so much
(between 1 or 5) then
the output is ok. This solve already a big problem that I had with the
DCM.
But now I see that sometimes the input and the output clock are
sometimes
not in phase and because of this I get now image on the screen or it
is wrong. You've got to "reload"
the signal and then the image appears or is it corrected. I already
tried to also reset
with the locked signal, but then I really don't works or is may clock
output from the DCM very strange.

A smaller thing, how higher the clock input is how smaller the output
signal comes, so at 160MHz
is maybe 500Mv from min to max. This stays the same if I change to the
HIGH mode.

Hope that someone nows how to solve it, of have a small tip for me
that would be very welcome
Thanks already

Greets
Pieter
Click to expand...
Check weather your FPGA device supports CLKIN range 40-160 MHZ.

What you are doing with DCM LOCKED_OUT signal? When CLKIN changes,
LOCKED_OUT signal will go low.
Once LOCKED_OUT signal goes low, reset should be asserted to DCM for a
minimum of 3 CLKIN cycles.
Please check weather you are doing this.

Regards,
JK
 
On 24 okt, 23:59, JK <krishna.januman...@gmail.com> wrote:
On Oct 24, 9:08 pm, Pieter <pieter.huy...@gmail.com> wrote:



Hi,

I hope anybody can solve my problem, i tried all many things to solve
it.
I've got the following problem:
In a vhdl design i implemented a DCM to make sure that a clock signal
is always 50% duty cycle at the output, so I thought that this would
be the easiest with a DCM, because it has an built in duty cycle
correction.
The major problem is that the input clock is variable between 40MHz
and 160MHz,
because I is used in an PC monitor with DVI input.
So everytime the frequency chances I will reset the DCM, at first I
worked very well
but sometime the output clock is not the same as the input clock. To
solve this I
wrote some code that counts some pulse from the incoming and the
outgoing clock.
Than I compare the two counters, if the difference is not so much
(between 1 or 5) then
the output is ok. This solve already a big problem that I had with the
DCM.
But now I see that sometimes the input and the output clock are
sometimes
not in phase and because of this I get now image on the screen or it
is wrong. You've got to "reload"
the signal and then the image appears or is it corrected. I already
tried to also reset
with the locked signal, but then I really don't works or is may clock
output from the DCM very strange.

A smaller thing, how higher the clock input is how smaller the output
signal comes, so at 160MHz
is maybe 500Mv from min to max. This stays the same if I change to the
HIGH mode.

Hope that someone nows how to solve it, of have a small tip for me
that would be very welcome
Thanks already

Greets
Pieter

Check weather your FPGA device supports CLKIN range 40-160 MHZ.

What you are doing with DCM LOCKED_OUT signal? When CLKIN changes,
LOCKED_OUT signal will go low.
Once LOCKED_OUT signal goes low, reset should be asserted to DCM for a
minimum of 3 CLKIN cycles.
Please check weather you are doing this.

Regards,
JK
Click to expand...
Hi,

I had already checked if my device supports the clock range, witch
is now problem for a spartan 3. I connected also the LOCKED_OUT signal
to the reset pin, but when I do that is just stays in reset.
Maybe it's better to explain how I now reset the DCM.
I've got two counters, one counts the incoming clock signal and the
other one counts the outgoing signal. With another clock I made a
window that is high for a time, in this time the counters will
count up with each rising edge of the in- or outgoing clock signal,
depends on the counter. Afther this period I will clock the two count
value in and compare them to each other. If the difference is more
than 10, then I will reset the DCM. I also added an counter that make
sure that the reset pin stays high for an certain amount of clock
cycles.
Also the DCM will reset when there's now dvi input signal anymore,
when status bit is high and there's also an external reset
possibility.

VHDL code:

fault_int <= (not dvisyncdetect or status(1)or DCMreset or
DCM_1_reset);
DCM_1_reset <= not (output_OK and DCM_locked) and delaycounter_int(9);

the output_OK is afther comparing the two counters and is the
difference
is to high then will output_OK be zero and is the output clock not
wright.
When I insert the above vhdl code, then the DCM will always be in
reset
mode and I don't get any output clock.

Hope you understanding a bit what I said

Greets
Pieter
 
On Oct 26, 2:21 pm, Pieter <pieter.huy...@gmail.com> wrote:
Hi,

I had already checked if my device supports the clock range, witch
is now problem for a spartan 3. I connected also the LOCKED_OUT signal
to the reset pin, but when I do that is just stays in reset.
Maybe it's better to explain how I now reset the DCM.
I've got two counters, one counts the incoming clock signal and the
other one counts the outgoing signal. With another clock I made a
window that is high for a time, in this time the counters will
count up with each rising edge of the in- or outgoing clock signal,
depends on the counter. Afther this period I will clock the two count
value in and compare them to each other. If the difference is more
than 10, then I will reset the DCM. I also added an counter that make
sure that the reset pin stays high for an certain amount of clock
cycles.
Also the DCM will reset when there's now dvi input signal anymore,
when status bit is high and there's also an external reset
possibility.

VHDL code:

fault_int <= (not dvisyncdetect or status(1)or DCMreset or
DCM_1_reset);
DCM_1_reset <= not (output_OK and DCM_locked) and delaycounter_int(9);

the output_OK is afther comparing the two counters and is the
difference
is to high then will output_OK be zero and is the output clock not
wright.
When I insert the above vhdl code, then the DCM will always be in
reset
mode and I don't get any output clock.

Hope you understanding a bit what I said

Greets
Pieter- Hide quoted text -

- Show quoted text -
Click to expand...

Analyze my code and revert back if you need clarification...

library IEEE;
use IEEE.std_logic_1164.ALL;
use IEEE.numeric_std.ALL;

-- Uncomment the following lines to use the declarations that are
-- provided for instantiating Xilinx primitive components.
library UNISIM;
use UNISIM.vcomponents.ALL;

entity test is
port (
clk : in std_logic;
reset : in std_logic;
clkout : out std_logic
);
end entity test;

architecture rtl of test is

component dcmclk
port (
clkin_in : in std_logic;
rst_in : in std_logic;
clkin_ibufg_out : out std_logic;
clk0_out : out std_logic;
locked_out : out std_logic
);
end component;

signal dcm_reset : std_logic;
signal dcm_reset_count : unsigned(3 downto 0);
signal lock : std_logic;
signal lock_reg : std_logic;
signal lock_fall_edge : std_logic;

begin
--instantiate DCM
Inst_dcmclk: dcmclk port map(
clkin_in => clk,
rst_in => dcm_reset,
clkin_ibufg_out => open,
clk0_out => clkout,
locked_out => lock
);

--find out loss of lock when clk changed with falling edge detection
process(clk, reset)
begin
if (reset='1') then
lock_reg <= '0';
elsif rising_edge(clk) then
lock_reg <= lock;
end if;
end process;
lock_fall_edge <= (not lock) and lock_reg;

--dcm reset generation
process(clk, reset)
begin
if (reset='1') then
dcm_reset <= '1';
dcm_reset_count <= 10;
elsif rising_edge(clk) then

-- step 1: normal operation, dcm starts functioning
dcm_reset <= '0';

-- step 2: dcm i/p changed, dcm lock lost
if (lock_fall_edge='1') then
--dcm reset is made high
dcm_reset <= '1';
--dcm reset count is initialized with 10
dcm_reset_count <= 10;
end if;

--step 3: next cycle, dcm reset down counter starts
if (dcm_reset='1') then
if (dcm_reset_count>0) then
dcm_reset_count <= dcm_reset_count-1;
dcm_reset <= '1';
end if;
end if;
-- when dcm reset counter is 0, dcm_reset is '0' -
same as step 1

end if;
end process;

end architecture rtl;
 
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