A
Arthur Sharp
Guest
Hi,
I have already used DCMs in real hw : a DDR controller on an Avnet board and
I got it to work. It used 3 DCM (2 for the DDR and another for something
else).
There were even cascaded.
Now, on a simpler design, I can't get it to lock. It simulates ok, synthesis
ok,
place and route ok, but the DCM does not lock. I can see that that's the
case
since I connected the lock signal to the LEDs on the board.
Basically, I have an SDRAM addition to the Avnet board. Because the clock
can only be provided by the FPGA, I need to make sure that clock and data
going out to the SDRAM have some reasonable skew to avoid set up and hold
time problems.
So, I simply anticipate the outgoing clock of about 1 ns using a DCM.
The output of the DCM is fed back to the CLK_FBK input through a
BUFG. It also goes out to a pad (after BUFG) through a FDDRSE primitive and
OBUF.
To see if there is a clock at all, this skewed clock is divided and
connected to a
LED on the board. The clock is there as the LED flashes.
However, it does not lock. The clock goes nowhere else : only to the divider
and
to the OBUF.
The clock is 40 MHz which is within the range specs for XC2V4000-4
(24-180 MHz) in low frequency mode.
This is much simpler than the DDR code and I'm going mental trying to find
out why.
Any ideas ? The code is pretty small and I could even post it here, there's
nothing
secret about it.
Please help,
Arthur
I have already used DCMs in real hw : a DDR controller on an Avnet board and
I got it to work. It used 3 DCM (2 for the DDR and another for something
else).
There were even cascaded.
Now, on a simpler design, I can't get it to lock. It simulates ok, synthesis
ok,
place and route ok, but the DCM does not lock. I can see that that's the
case
since I connected the lock signal to the LEDs on the board.
Basically, I have an SDRAM addition to the Avnet board. Because the clock
can only be provided by the FPGA, I need to make sure that clock and data
going out to the SDRAM have some reasonable skew to avoid set up and hold
time problems.
So, I simply anticipate the outgoing clock of about 1 ns using a DCM.
The output of the DCM is fed back to the CLK_FBK input through a
BUFG. It also goes out to a pad (after BUFG) through a FDDRSE primitive and
OBUF.
To see if there is a clock at all, this skewed clock is divided and
connected to a
LED on the board. The clock is there as the LED flashes.
However, it does not lock. The clock goes nowhere else : only to the divider
and
to the OBUF.
The clock is 40 MHz which is within the range specs for XC2V4000-4
(24-180 MHz) in low frequency mode.
This is much simpler than the DDR code and I'm going mental trying to find
out why.
Any ideas ? The code is pretty small and I could even post it here, there's
nothing
secret about it.
Please help,
Arthur
