dcm error

Z

zlotawy

Guest
Hello,
I have problem. I'd like to use DCM. I generated it by creator.

'library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
-- synopsys translate_off
library UNISIM;
use UNISIM.Vcomponents.ALL;
-- synopsys translate_on

entity ll is

port ( CLKIN_IN : in std_logic;
RST_IN : in std_logic;
CLKFX_OUT : out std_logic;
CLKIN_IBUFG_OUT : out std_logic;
CLK0_OUT : out std_logic;
LOCKED_OUT : out std_logic);
end ll;

architecture BEHAVIORAL of ll is
signal CLKFB_IN : std_logic;
signal CLKFX_BUF : std_logic;
signal CLKIN_IBUFG : std_logic;
signal CLK0_BUF : std_logic;
signal GND1 : std_logic;
component BUFG
port ( I : in std_logic;
O : out std_logic);
end component;

component IBUFG
port ( I : in std_logic;
O : out std_logic);
end component;


component DCM

port ( CLKIN : in std_logic;
CLKFB : in std_logic;
RST : in std_logic;
PSEN : in std_logic;
PSINCDEC : in std_logic;
PSCLK : in std_logic;
DSSEN : in std_logic;
CLK0 : out std_logic;
CLK90 : out std_logic;
CLK180 : out std_logic;
CLK270 : out std_logic;
CLKDV : out std_logic;
CLK2X : out std_logic;
CLK2X180 : out std_logic;
CLKFX : out std_logic;
CLKFX180 : out std_logic;
STATUS : out std_logic_vector (7 downto 0);
LOCKED : out std_logic;
PSDONE : out std_logic);
end component;

begin
GND1 <= '0';
CLKIN_IBUFG_OUT <= CLKIN_IBUFG;
CLK0_OUT <= CLKFB_IN;
CLKFX_BUFG_INST : BUFG
port map (I=>CLKFX_BUF,
O=>CLKFX_OUT);

CLKIN_IBUFG_INST : IBUFG
port map (I=>CLKIN_IN,
O=>CLKIN_IBUFG);

CLK0_BUFG_INST : BUFG
port map (I=>CLK0_BUF,
O=>CLKFB_IN);

DCM_INST : DCM

port map (CLKFB=>CLKFB_IN,
CLKIN=>CLKIN_IBUFG,
DSSEN=>GND1,
PSCLK=>GND1,
PSEN=>GND1,
PSINCDEC=>GND1,
RST=>RST_IN,
CLKDV=>open,
CLKFX=>CLKFX_BUF,
CLKFX180=>open,
CLK0=>CLK0_BUF,
CLK2X=>open,
CLK2X180=>open,
CLK90=>open,
CLK180=>open,
CLK270=>open,
LOCKED=>LOCKED_OUT,
PSDONE=>open,
STATUS=>open);

end BEHAVIORAL;"


when I synthesise it, I receive message error: "No default binding for
component: <DCM>. Ports
<CLKIN,CLKFB,RST,PSEN,PSINCDEC,PSCLK,DSSEN,CLK0,CLK90,CLK180,CLK270,CLKDV,CLK2X,
CLK2X180,CLKFX,CLKFX180,STATUS,LOCKED,PSDONE> are not on the entity.".
What does it mean? Something bad with library?

Thanks,
Wojtek
 
On Jun 9, 2:06 pm, "zlotawy" <spaw...@wp.NO_SPAM.pl> wrote:
Hello,
I have problem. I'd like to use DCM. I generated it by creator.

'library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
-- synopsys translate_off
library UNISIM;
use UNISIM.Vcomponents.ALL;
-- synopsys translate_on

entity ll is

port ( CLKIN_IN : in std_logic;
RST_IN : in std_logic;
CLKFX_OUT : out std_logic;
CLKIN_IBUFG_OUT : out std_logic;
CLK0_OUT : out std_logic;
LOCKED_OUT : out std_logic);
end ll;

architecture BEHAVIORAL of ll is
signal CLKFB_IN : std_logic;
signal CLKFX_BUF : std_logic;
signal CLKIN_IBUFG : std_logic;
signal CLK0_BUF : std_logic;
signal GND1 : std_logic;
component BUFG
port ( I : in std_logic;
O : out std_logic);
end component;

component IBUFG
port ( I : in std_logic;
O : out std_logic);
end component;

component DCM

port ( CLKIN : in std_logic;
CLKFB : in std_logic;
RST : in std_logic;
PSEN : in std_logic;
PSINCDEC : in std_logic;
PSCLK : in std_logic;
DSSEN : in std_logic;
CLK0 : out std_logic;
CLK90 : out std_logic;
CLK180 : out std_logic;
CLK270 : out std_logic;
CLKDV : out std_logic;
CLK2X : out std_logic;
CLK2X180 : out std_logic;
CLKFX : out std_logic;
CLKFX180 : out std_logic;
STATUS : out std_logic_vector (7 downto 0);
LOCKED : out std_logic;
PSDONE : out std_logic);
end component;

begin
GND1 <= '0';
CLKIN_IBUFG_OUT <= CLKIN_IBUFG;
CLK0_OUT <= CLKFB_IN;
CLKFX_BUFG_INST : BUFG
port map (I=>CLKFX_BUF,
O=>CLKFX_OUT);

CLKIN_IBUFG_INST : IBUFG
port map (I=>CLKIN_IN,
O=>CLKIN_IBUFG);

CLK0_BUFG_INST : BUFG
port map (I=>CLK0_BUF,
O=>CLKFB_IN);

DCM_INST : DCM

port map (CLKFB=>CLKFB_IN,
CLKIN=>CLKIN_IBUFG,
DSSEN=>GND1,
PSCLK=>GND1,
PSEN=>GND1,
PSINCDEC=>GND1,
RST=>RST_IN,
CLKDV=>open,
CLKFX=>CLKFX_BUF,
CLKFX180=>open,
CLK0=>CLK0_BUF,
CLK2X=>open,
CLK2X180=>open,
CLK90=>open,
CLK180=>open,
CLK270=>open,
LOCKED=>LOCKED_OUT,
PSDONE=>open,
STATUS=>open);

end BEHAVIORAL;"

when I synthesise it, I receive message error: "No default binding for
component: <DCM>. Ports
CLKIN,CLKFB,RST,PSEN,PSINCDEC,PSCLK,DSSEN,CLK0,CLK90,CLK180,CLK270,CLKDV,C­LK2X,
CLK2X180,CLKFX,CLKFX180,STATUS,LOCKED,PSDONE> are not on the entity.".
What does it mean? Something bad with library?

Thanks,
Wojtek
Click to expand...
Have you added dcm.xaw to the Project???

Regards,
JK
 
Uzytkownik "JK" <krishna.janumanchi@gmail.com> napisal w wiadomosci
news:1181407166.704545.43980@g37g2000prf.googlegroups.com...
Wojtek
Click to expand...
Have you added dcm.xaw to the Project???



Yes. It is parallel to main entity.

zlotawy
 
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