[DC ASIC] Why more area == good timing?

[Davy]

Hi all,

My friend told me if you want to get good timing, you have to make the
ASIC with more area, is it right?

By the way, I have read a book(Advanced.ASIC.Chip.Synthesis), it said
"For overly constrained design, DC tries to synthesize "Vertical logic"
to meet the tight timing constraints.

Vertical logic:
***
* *
* *
* *
***



Is "Vertical logic" equal to more area and good timing?

Best regards,
Davy

 

[Winfield Hill]

Davy wrote...

My friend told me if you want to get good timing, you have to make the
ASIC with more area, is it right?

By the way, I have read a book(Advanced.ASIC.Chip.Synthesis), it said
"For overly constrained design, DC tries to synthesize "Vertical logic"
to meet the tight timing constraints.

Vertical logic:
***
* *
* *
* *
***

Is "Vertical logic" equal to more area and good timing?

boki?


--
Thanks,
- Win

 

[Pulzar]

It depends on what kind of logic is in your critical path, but that is
true in general. Usually, your slowest cells are the ones driving
either long wires or multiple cells -- in order to make the faster,
i.e. reduce their gate delay, you have to make their drivers larger,
which increases the chip area.


Davy wrote:

Hi all,

My friend told me if you want to get good timing, you have to make the
ASIC with more area, is it right?

By the way, I have read a book(Advanced.ASIC.Chip.Synthesis), it said
"For overly constrained design, DC tries to synthesize "Vertical logic"
to meet the tight timing constraints.

Vertical logic:
***
* *
* *
* *
***



Is "Vertical logic" equal to more area and good timing?

Best regards,
Davy

 

[hnain.said@gmail.com]

hi Davy,

I want to give a simple example to understand the famous trade-off
between area and speed, if we suppose that we want to do the operation
: s= a.x+b.y+c.z

if we implement one multiplier and one adder we will need at least 3
clock cycles to calculate s, but the area is small.
if we implement 3 multipliers and 3 adders the latency will be minimal
(hardware operation) less than one clock cycle, but the area is bigest.

best regards
Said HNAIN (Morocco)

 

[krw]

In article <1149239075.115382.99710@i40g2000cwc.googlegroups.com>,
zhushenli@gmail.com says...

Hi all,

My friend told me if you want to get good timing, you have to make the
ASIC with more area, is it right?

Often, but not always.

By the way, I have read a book(Advanced.ASIC.Chip.Synthesis), it said
"For overly constrained design, DC tries to synthesize "Vertical logic"
to meet the tight timing constraints.

Vertical logic:
***
* *
* *
* *
***

^
|
+---- This is your delay

Is "Vertical logic" equal to more area and good timing?

Equal to? Not necessarily. There are several things that can be
done to make timing. As has been pointed out already, one may do
work in parallel so the slowest path is shorter or increase device
size to improve delay.

One can also duplicate logic to reduce loading or wire length.
Sometimes pipeline stages are added/modified to make the work fit
the timing. Often buffers are inserted to reduce delays on long
lines. ...lotsa knobs to turn to make timing.
--
Keith