C
Chloe
Guest
Dear everyone,
I'd like to know, in Verilog system tasks, is there any way to
timestamp and datestamp output files?
My design has a testbench which outputs different simulation times to
an output file (let's call it output.log). Is there any way for me to
also insert the date and time of start of simulation onto the output
file? I have different output files which I need to inspect after a
long simulation period, and it would be really useful if I know when
the simulations were carried out.
Please let me know if you have further questions, in case I am not
clear in my question.
Thanks very much.
Chloe
I'd like to know, in Verilog system tasks, is there any way to
timestamp and datestamp output files?
My design has a testbench which outputs different simulation times to
an output file (let's call it output.log). Is there any way for me to
also insert the date and time of start of simulation onto the output
file? I have different output files which I need to inspect after a
long simulation period, and it would be really useful if I know when
the simulations were carried out.
Please let me know if you have further questions, in case I am not
clear in my question.
Thanks very much.
Chloe